Semiconductor Package UBM Layout to Prevent Edge Damage
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Solution Overview
Problem
The reliability of semiconductor packages is compromised due to damage at the edges of the under bump metallurgy (UBM) caused by differences in physical properties between the photoimageable dielectric (PID) material and the UBM.
Innovation Solution
A semiconductor package design where the redistribution substrate includes a first and second insulating layer, with the UBM formed prior to the redistribution layer (RDL), ensuring that the metal pattern is not in contact with the second insulating layer, thereby reducing damage from thermal expansion differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the UBM is formed after the PID material is deposited, then the manufacturing process follows conventional sequence, but the edge of the UBM becomes damaged due to difference in physical properties between PID and UBM
Solution Approach 1:
The under bump metallurgy (UBM) is formed before the photoimageable dielectric (PID) material is deposited and cured. This preliminary formation of UBM prevents the UBM edges from being damaged by the PID material, as the UBM is already in place and protected when the PID process occurs. The manufacturing sequence is inverted from the conventional approach where UBM is formed after PID deposition.
2Reliability
If the metal pattern is in contact with the second insulating layer, then the structure is simplified, but thermal expansion differences cause damage to the UBM
Solution Approach 1:
The patent introduces a specific structural arrangement where the metal pattern is positioned such that it does not directly contact the second insulating layer. Instead, the metal pattern is separated by the curvature of the first insulating layer and the positioning of the redistribution pattern, which acts as an intermediary structure. This intermediary arrangement prevents direct contact between the metal pattern and second insulating layer, thereby avoiding damage from thermal expansion differences while maintaining structural integrity.
3Reliability
If the redistribution pattern is formed to contact the metal pattern sidewalls, then electrical connection is improved, but the manufacturing precision requirement increases
Solution Approach 1:
The patent employs a curved surface design for the first insulating layer that dynamically adapts to accommodate variations in manufacturing. The curvature of the first insulating layer creates a flexible interface between the UBM and the redistribution pattern, allowing for tolerance compensation. This dynamic geometric design enables the redistribution pattern to contact the metal pattern sidewalls reliably without requiring extremely tight manufacturing precision, as the curved surface provides a degree of geometric flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and performance of the semiconductor package by minimizing damage to the UBM and improving the structural integrity of the package.
Implementation Method 1
a metal pattern electrically connected to the redistribution pattern
Implementation Method 2
damage is incurred at an edge of an under bump metallurgy (UBM) due to the difference in physical properties between a photoimageable dielectric (PID) material and the UBM
Data Source
AI summary
A semiconductor package includes a redistribution substrate including a first surface and a second surface, which are opposite to each other in a first direction, a semiconductor chip mounted on the first surface of the redistribution substrate, a redistribution pattern in the redistribution substrate and electrically connected to the semiconductor chip, a metal pattern electrically connected to the redistribution pattern, including a third surface and a fourth surface, which are opposite to each other in the first direction, and a connection terminal on the second surface of the redistribution substrate and being in contact with the fourth surface of the metal pattern, wherein at least a portion of the redistribution pattern is in contact with sidewalls of the metal pattern, wherein the third surface faces the semiconductor chip and is not in contact with the redistribution pattern, and wherein the fourth surface does not overlap the second surface in the first direction.