3D Semiconductor Package UBM Layout for Stress-Resilient Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving higher integration density, smaller size for unit performance, and ensuring reliability as the integration density increases, with under bump metallurgy (UBM) being a bottleneck for securing reliability.
Innovation Solution
A semiconductor package structure is designed with multiple redistribution layers and insulating layers, featuring conductive posts and UBM structures that overlap and connect to distribute mechanical and thermodynamic stress, along with an impedance element encapsulated by an encapsulant to enhance electrical connections and reduce stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density of the semiconductor package is increased or size is reduced for the same unit performance, then productivity and performance are improved, but the degree of difficulty in securing reliability increases
Solution Approach 1:
The patent transitions from a planar redistribution layer structure to a three-dimensional structure by extending UBM patterns vertically along conductive posts and creating overlapping regions between upper and lower UBM structures. This dimensional change allows stress to be distributed throughout the vertical depth of the package rather than being concentrated in a single plane, thereby maintaining reliability while achieving higher integration density.
Solution Approach 2:
The patent employs a composite structure combining multiple materials with different mechanical and electrical properties: conductive posts (metal), UBM structures (metallurgical layer), encapsulant (polymer or ceramic), and substrate (printed circuit board). This composite approach allows each material to contribute its optimal properties - the conductive posts provide mechanical support and electrical conductivity, the UBM ensures reliable electrical connection, and the encapsulant provides mechanical protection and stress distribution, collectively solving the reliability challenge in high-density packages.
2Reliability
If redistribution layers are extended horizontally to connect bumps vertically, then electrical connection path is extended, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by transitioning from horizontal extension of redistribution layers to vertical extension through conductive posts and overlapping UBM structures. Instead of spreading redistribution layers across a large horizontal area to achieve bump connections, the invention uses vertical conductive posts that extend upward from lower UBM structures, with upper UBM structures overlapping these posts. This vertical approach achieves the same electrical connection function with less horizontal footprint and simpler redistribution layer routing.
Data Source
AI summary
A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.