Semiconductor Package Via Layout for UBM Stress Relief
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Solution Overview
Problem
Semiconductor packages face challenges in maintaining reliability due to delamination or cracking caused by thermal stress and external impacts, particularly due to stress concentration on redistribution vias and UBM layers during soldering processes.
Innovation Solution
The semiconductor package design includes a redistribution structure with a specific arrangement of redistribution vias and UBM layers, where the top redistribution via is positioned to overlap a central point of the UBM layer rather than the UBM vias, reducing stress concentration and enhancing reliability by distributing stress more evenly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the redistribution via is positioned to overlap the UBM vias, then the electrical connection is simplified, but stress concentration occurs causing delamination or cracking
Solution Approach 1:
The redistribution via is deliberately positioned asymmetrically relative to the UBM vias, specifically overlapping the central region rather than aligning with individual UBM vias. This asymmetric positioning redistributes the stress field and prevents stress concentration at via interfaces, thereby maintaining reliability while preserving electrical connectivity.
Solution Approach 2:
The solution transitions from a one-to-one vertical alignment relationship between redistribution vias and UBM vias to a distributed overlapping pattern where the redistribution via spans across multiple UBM vias in the planar dimension. This dimensional redistribution of the via position resolves the stress concentration issue while maintaining electrical connection functionality.
2Reliability
If the redistribution via overlaps the UBM layer central region, then stress is distributed evenly improving reliability, but the electrical connection path becomes more complex
Solution Approach 1:
The via positioning strategy applies local quality by creating different functional zones: the central region of the UBM layer serves as a stress-distribution zone where the redistribution via overlaps, while the peripheral UBM vias maintain their individual connection functions. This localized differentiation optimizes both reliability and electrical connectivity.
3Ease of manufacture
If conventional via positioning is used, then manufacturing is simpler, but thermal stress and external impacts cause delamination or cracking
Solution Approach 1:
The redistribution via is pre-positioned to overlap the central region of the UBM layer before thermal stress or external impacts occur. This preliminary positioning creates a stress-distribution configuration that actively counteracts the harmful effects of thermal expansion and mechanical impacts, preventing delamination and cracking before they can initiate.
Data Source
AI summary
A semiconductor package includes: a redistribution structure having a first surface and a second surface and including a plurality of redistribution layers, the plurality of redistribution layers including first and second redistribution layers adjacent to the first and second surfaces, respectively,; a semiconductor chip disposed on the first surface; a frame including a wiring structure connected to a first redistribution via of the first redistribution layer; and UBM layers disposed on the second surface and having a plurality of UBM vias. The UBM layers may include at least one UBM layer overlapping the first redistribution via, and the first redistribution via may be disposed so as not to overlap a plurality of UBM vias of the at least one UBM layer and to overlap an internal region closer to a central point of the at least one UBM layer than the plurality of UBM vias.