Semiconductor Package Trace Layout for Void-Free Underfill Flow
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Solution Overview
Problem
The increasing complexity of solder joint arrays in semiconductor devices leads to obstructed underfill flow during manufacturing, resulting in voids that weaken solder joints due to the layout of metal traces in the substrate.
Innovation Solution
Introduce gaps in longer traces oriented perpendicular to the direction of underfill flow using vias to route traces through a lower layer, or reorient longer traces parallel to the underfill flow direction to minimize obstructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the solder joint array complexity increases to accommodate higher storage capacity, then the storage capacity and functionality improve, but the metal trace layout becomes more complex and obstructs underfill flow
Solution Approach 1:
The patent segments the metal trace layout by introducing gaps in longer traces oriented perpendicular to underfill flow direction. These gaps break continuous trace structures into separate segments, allowing underfill material to flow through areas that would otherwise be blocked by solid metal traces, thus resolving the conflict between maintaining complex trace layouts for high storage capacity and enabling proper underfill flow.
2Reliability
If longer traces are used to accommodate increased solder joints, then the electrical connectivity improves, but the underfill flow is obstructed leaving voids
Solution Approach 1:
The patent applies local quality by selectively modifying only specific trace regions where gaps are introduced in longer traces perpendicular to underfill flow, while maintaining continuous traces in other areas. This localized modification allows underfill to flow through previously obstructed areas without compromising the overall electrical connectivity provided by the trace network.
Solution Approach 2:
The patent addresses the two-dimensional trace layout problem by considering the third dimension of underfill flow. By introducing gaps in traces perpendicular to the flow direction, the patent creates flow pathways that utilize the available space more effectively, allowing underfill to distribute uniformly across the substrate surface without being blocked by the planar trace configuration.
3Ease of manufacture
If traces are reoriented parallel to underfill flow, then underfill flow obstruction decreases, but trace routing complexity may increase
Solution Approach 1:
Rather than completely reorienting all traces parallel to underfill flow, the patent segments the trace network and introduces gaps in perpendicular traces. This approach achieves the benefit of reduced flow obstruction while maintaining the original trace routing orientation, avoiding the complexity of complete reorientation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces underfill voids, ensuring consistently strong solder joint arrays by improving underfill flow, enhancing the reliability and quality of semiconductor devices.
Implementation Method 1
An underfill material may reduce thermal stresses on the solder joints and corresponding metal contacts
Data Source
AI summary
A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.