Semiconductor Package Recess Underfill for Wire Bond Reliability
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Solution Overview
Problem
The existing wire bonding process for semiconductor packages faces challenges in improving bonding strength and reliability due to physical forces applied during the formation of additional bumps, which can lead to defects like leakage and shorts, and limited enhancement of bonding area.
Innovation Solution
A semiconductor package design that includes a package substrate with a recessed area exposing substrate pads, a dam structure surrounding the recess, stacked semiconductor chips, bonding wires connecting chip pads to substrate pads, and an underfill member filling the recess to cover the bonding wires and substrate pads, thereby enhancing bonding reliability without applying physical force.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an additional bump is formed on a bonding portion of the metal wire to increase bondability, then bonding strength is improved, but the metal wire contacts the side of stacked semiconductor chips causing leakage and short of current
Solution Approach 1:
The patent transitions from horizontal wire bonding to vertical wire bonding by forming via holes through the substrate. This dimensional change allows wires to connect to chip pads from below without contacting the side surfaces of stacked chips, eliminating the harmful contact while maintaining bonding strength through the vertical connection path.
Solution Approach 2:
The substrate is segmented by forming multiple via holes at different locations to separately connect different chip pads. This segmentation allows independent wire routing to each pad without interference, preventing short circuits while maintaining individual bonding strength for each connection.
2Strength
If an additional bump is formed on a bonding portion of the metal wire to increase bondability, then bonding strength is improved, but the process does not increase actual bonding area of the metal wire
Solution Approach 1:
The patent increases bonding area by utilizing the vertical dimension through via holes. Multiple wires can be bundled and connected to chip pads through the substrate thickness, effectively increasing the bonding area in three-dimensional space rather than being limited to a two-dimensional surface bump.
Solution Approach 2:
Multiple bonding wires are nested together within the via holes of the substrate, allowing them to be bundled and connected to the chip pad simultaneously. This nesting increases the effective bonding area by stacking wire connections vertically rather than spreading them horizontally.
3Reliability
If wire bonding is performed on stacked chips, then electrical connection is achieved, but physical force during bump formation causes defects
Solution Approach 1:
Instead of forming bumps on top of the wires (conventional approach), the patent inverts the process by forming via holes through the substrate and allowing wires to grow or be deposited from the bottom side. This inversion eliminates the need for bump formation that applies physical force, thereby preventing defects while achieving reliable electrical connection.
Solution Approach 2:
The substrate with via holes acts as an intermediary structure that facilitates wire connection to chip pads without requiring direct bump formation on the wires. The via holes provide a controlled pathway that mediates the connection process, eliminating harmful physical forces while ensuring reliable electrical connection.
Data Source
AI summary
A semiconductor package includes a package substrate having substrate pads spaced apart from each other in a first direction and an upper insulation layer on an upper surface of the package substrate, the upper insulation layer defining a recess that exposes the substrate pads; a dam structure extending on the upper insulation layer to surround the recess; semiconductor chips stacked on the upper insulation layer of the package substrate such that a first surface on which chip pads are formed faces upward, semiconductor chips spaced apart from the dam structure in a second direction perpendicular to the first direction; bonding wires connecting the substrate pads to the chip pads of the semiconductor chips; and an underfill member filling an interior of the recess to cover an end portion of each of the bonding wires and each of the substrate pads.