Semiconductor Package Through-Hole Layout for Underfill Void Suppression
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Solution Overview
Problem
In semiconductor packaging, the formation of voids in the under-fill layer between the substrate and the semiconductor chip can lead to reduced reliability and integration density, especially as the complexity and density of conductive patterns increase.
Innovation Solution
The introduction of through holes in the substrate between conductive patterns, which are partially filled by the under-fill layer, helps to suppress void formation by allowing air evacuation during the under-fill layer formation process, thereby enhancing the integration density and reliability of the semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the degree of integration of conductive patterns is increased, then the wiring density is improved, but voids are more easily formed in the under-fill layer
Solution Approach 1:
The substrate is segmented by forming through holes that penetrate it, dividing the space between substrate and semiconductor chip into multiple regions. This segmentation allows the under-fill layer to be applied in a controlled manner, preventing void formation even when wiring density is high.
Solution Approach 2:
Through holes act as intermediary structures that facilitate the application of under-fill layer. These holes provide pathways for the under-fill material to reach and fill spaces between conductive patterns, ensuring complete coverage without voids in high-density wiring configurations.
2Reliability
If through holes are formed between conductive patterns, then voids are suppressed in the under-fill layer, but the manufacturing process becomes more complex
Solution Approach 1:
Through holes are formed in the substrate before the under-fill layer is applied. This preliminary action prepares the structure in advance, creating pathways that guide the under-fill material during subsequent application, thereby preventing void formation without requiring complex real-time processing.
Solution Approach 2:
The substrate is transformed into a porous structure with through holes, which facilitates the infiltration and uniform distribution of the under-fill layer. This porous design simplifies the manufacturing process by allowing the under-fill material to naturally flow into and fill spaces, reducing the need for complex filling operations.
3Reliability
If through holes are formed in the substrate, then under-fill layer voids are reduced, but additional manufacturing steps are required
Solution Approach 1:
The formation of through holes is merged with other substrate processing steps, such as patterning or etching operations already performed during semiconductor manufacturing. By combining multiple functions into a single process step, the addition of through holes does not significantly increase the total number of manufacturing steps.
Solution Approach 2:
The substrate structure is modified by changing its physical parameters - specifically, by creating through holes with specific dimensions and distributions. This parameter change enables the substrate to better accommodate the under-fill layer, improving quality while requiring minimal additional processing steps.
Data Source
AI summary
A semiconductor package includes: a substrate including a chip region and an edge region extending around the chip region; a plurality of film wirings on the substrate in the chip region; an input wiring and an output wiring on the substrate in the edge region and extending to the chip region in a direction parallel to an upper surface of the substrate; and a semiconductor chip on the substrate in the chip region and electrically connected to the input wiring and the output wiring. The substrate includes a through hole extending through the substrate in a second direction perpendicular to the first direction, and the through hole is between the film wirings.