Stacked Semiconductor Package Layout for Uniform CMP and Bonding
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high reliability due to variations in metal densities between main and edge regions, leading to uneven CMP removal rates and potential voids in dielectric layers, which affect bonding strength and overall package reliability.
Innovation Solution
The semiconductor package design includes dummy pads on the edge region with the same material as main pads, ensuring similar metal densities across both regions, and a specific spacing and thickness configuration of dielectric layers to maintain consistent CMP removal rates, thereby preventing voids and enhancing bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used without dummy pads, then the manufacturing process is simpler, but metal density variations cause uneven CMP removal rates and voids in dielectric layers
Solution Approach 1:
The patent applies the copying principle by creating dummy pads that replicate the structure and material composition of main pads. These dummy pads are positioned in edge regions to copy the metal density characteristics of functional pads, thereby uniforming the overall metal distribution across the semiconductor chip surface and ensuring consistent CMP removal rates without adding complex functional elements.
Solution Approach 2:
The patent implements local quality by strategically placing dummy pads specifically in edge regions where metal density is naturally lower. This localized addition of conductive structures modifies the metal distribution only where needed, maintaining the simplicity of the main chip area while correcting the density imbalance at the edges to prevent void formation during CMP processing.
2Manufacturing precision
If dummy pads are added to uniform metal density, then CMP removal rates become consistent, but the package structure becomes more complex
Solution Approach 1:
The dummy pads are designed as simplified copies of main pads, replicating only the essential conductive structure and material composition needed to adjust metal density. This copying approach achieves CMP uniformity without requiring complex multi-layer or multi-material structures, maintaining manufacturing precision while minimizing structural complexity.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the number, size, and positioning of dummy pads to optimize metal density distribution. By varying these parameters, the design achieves consistent CMP removal rates across different chip regions without necessitating fundamental changes to the pad structure or material composition, thereby balancing manufacturing precision with structural simplicity.
3Reliability
If wiring layer thickness is increased on main region, then electrical performance improves, but edge region metal density becomes insufficient causing voids
Solution Approach 1:
The patent applies local quality by adding dummy pads specifically in edge regions to compensate for the lower metal density in those areas. This localized enhancement ensures that while the main region maintains its optimized wiring layer thickness for electrical performance, the edge regions achieve sufficient metal density to prevent void formation during CMP processing, thereby maintaining bonding strength across the entire chip.
Solution Approach 2:
The dummy pads act as a counterweight to the metal density deficiency in edge regions. By adding these conductive structures, the patent balances the overall metal distribution across the chip, compensating for the relative scarcity of metal in edge areas compared to the main region, thus preventing voids and ensuring uniform bonding quality.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first main region and a first edge region, and a second semiconductor chip on the first semiconductor chip and including a second main region and a second edge region. The first semiconductor chip includes a first main pad and a first dummy pad respectively on the first main region and the first edge region on a top surface of the first semiconductor chip. The second semiconductor chip includes a first semiconductor substrate, a wiring layer below the first semiconductor substrate and including a wiring dielectric layer and wiring patterns, a second main pad and a second dummy pad respectively on the second main region and the second edge region below the wiring layer. A thickness of the wiring layer is greater on the second main region than on the second edge region.