Semiconductor Package Warpage Mitigation via Variable Chip Thickness
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Solution Overview
Problem
Semiconductor packages face warpage issues due to differences in chip thicknesses, leading to connection defects between stacked chips, which affect the performance and reliability of electronic devices.
Innovation Solution
The semiconductor package design involves varying the thicknesses of stacked chips, with specific adjustments to the second, third, and fourth chips' thicknesses to mitigate warpage, using a four-level or higher stacking process where the second and fourth chips' thicknesses are increased, and the third chip's thickness is reduced, while the fifth chip has no through vias, and a package molding part surrounds the chips to protect and secure them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform thickness chips are stacked, then manufacturing is simpler, but warpage occurs leading to connection defects
Solution Approach 1:
The patent applies local quality by varying the thickness of specific chips in the stack based on their position. Chips closer to the center of the stack have different thicknesses compared to those at the edges, creating a non-uniform thickness distribution that compensates for warpage effects and improves connection reliability between stacked chips.
Solution Approach 2:
The patent changes the physical parameter of chip thickness to resolve the warpage issue. By adjusting the thickness parameter of individual chips in the stack, the overall structural balance is improved, reducing warpage and preventing connection defects while maintaining manufacturing feasibility.
2Reliability
If chip thicknesses are varied to reduce warpage, then connection reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the chip stack into different groups based on position, with each group having optimized thickness characteristics. This segmentation allows for controlled thickness variation across the stack while maintaining manageable manufacturing precision requirements for each segment rather than requiring extreme precision across all chips.
Solution Approach 2:
The patent implements controlled parameter changes in chip thickness as a design specification rather than a manufacturing tolerance challenge. By pre-determining the thickness variations needed for warpage compensation, the manufacturing process can target specific thickness values with standard precision, avoiding the need for excessive manufacturing precision.
3Productivity
If more chips are stacked to increase capacity, then device functionality improves, but warpage and connection defects increase
Solution Approach 1:
The patent applies local quality principles to multi-chip stacks by optimizing the thickness of chips at different positions within the stack. This position-dependent thickness optimization reduces warpage effects that would otherwise accumulate with increased stacking height, enabling higher device capacity while maintaining connection reliability.
Solution Approach 2:
The patent uses parameter changes in chip thickness as a scaling solution for multi-chip stacks. As the number of stacked chips increases to improve device capacity, the thickness parameter of individual chips is adjusted to compensate for increased warpage risks, allowing productivity improvement without sacrificing reliability.
Data Source
AI summary
A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.