Semiconductor Package With Vertical Capacitor for Fast DRAM Discharge
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Solution Overview
Problem
In semiconductor chip packages, particularly for DRAM chips, the current path from the de-coupling capacitor to the chip is too long, leading to delayed discharge during power-intensive operations, resulting in chip failure.
Innovation Solution
The semiconductor package design includes a capacitor positioned to overlap the chip vertically, with a conductive path optimized by a conductive line and molding compounds, ensuring rapid discharge and enhanced filtering efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the de-coupling capacitor is located on the same surface of the substrate as the chip, then the package structure is simple, but the current path is too long causing delayed discharge and chip failure
Solution Approach 1:
The patent transitions the capacitor placement from a two-dimensional surface layout to a three-dimensional vertical stacking arrangement. The capacitor is positioned on the opposite surface of the substrate and electrically connected to the chip through conductive structures, creating a vertical current path that significantly reduces the discharge path length while maintaining package simplicity
Solution Approach 2:
The patent embeds the capacitor within the substrate structure by routing conductive lines through the substrate thickness. The capacitor is nested in relation to the chip, with the substrate acting as an intermediary that provides both mechanical support and electrical connection pathways, effectively integrating both components into a compact three-dimensional architecture
2Speed
If the capacitor is placed close to the chip to reduce current path length, then the discharge speed improves, but the available space on the substrate is limited
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) to place the capacitor on the opposite surface from the chip. This vertical separation allows both components to be positioned at extreme ends of the substrate, maximizing their spacing in the planar direction while minimizing the current path length through the substrate thickness, thereby achieving fast discharge without consuming additional substrate area
Data Source
AI summary
A semiconductor package includes a substrate, a chip, a capacitor, a first molding compound and a second molding compound. The substrate has a first surface, a second surface and an opening, wherein the first surface is opposite to the second surface. The chip is located on the first surface of the substrate and in the opening of the substrate. The capacitor overlaps the chip in a vertical direction and electrically connected to the chip. A first molding compound covers the chip and the first surface of the substrate. The second molding compound covers the capacitor and the second surface of the substrate.