Stacked Semiconductor Package With Vertical Heat Dissipation Path
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Solution Overview
Problem
Stacked semiconductor packages face challenges in heat dissipation due to the upper semiconductor package obstructing heat dissipation in the upper direction, leading to deteriorated thermal management as integration increases.
Innovation Solution
Incorporating a heat source mark and a heat dissipation member at the second region of the first semiconductor package, which overlaps the higher power element in a vertical direction, enhancing heat dissipation efficiency and using the heat source mark as an alignment mark for proper placement of the heat dissipation member.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an upper semiconductor package is stacked on a lower semiconductor package to achieve miniaturization and high integration, then the device size is reduced and integration is increased, but the heat dissipation property in the upper direction deteriorates
Solution Approach 1:
The patent introduces a new spatial dimension for heat dissipation by placing a heat dissipation member in the second region that extends in the vertical direction (perpendicular to the in-plane direction). This allows heat to be dissipated not only in the lateral direction but also in the vertical dimension, effectively adding another heat dissipation pathway that does not conflict with the stacked package structure.
Solution Approach 2:
The patent applies local quality by concentrating heat dissipation resources specifically in the second region where high-power elements are located. The heat dissipation member is positioned to overlap with the high-power element in the vertical direction, providing enhanced heat dissipation capacity precisely where it is most needed, rather than uniformly distributing heat dissipation structures across the entire device.
2Temperature
If heat dissipation structures are added to improve thermal management, then heat dissipation performance is improved, but device complexity increases
Solution Approach 1:
The heat source mark serves multiple functions: it identifies the location of high-power elements for heat dissipation purposes, acts as an alignment mark for positioning the heat dissipation member during manufacturing, and can potentially serve as a bonding interface. This multi-functionality reduces the need for separate dedicated alignment marks and simplifies the overall device structure.
Solution Approach 2:
The heat source mark inherently provides alignment functionality without requiring additional separate alignment structures. The same feature that identifies heat generation locations (the heat source mark) also serves as the reference for positioning heat dissipation components, allowing the structure to serve its own alignment needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively radiates heat from the semiconductor chip, improving heat dissipation performance and reliability of the stacked semiconductor package while efficiently using space with the second semiconductor package and through connecting portion.
Implementation Method 1
heat of a semiconductor chip included in a first semiconductor package disposed at a lower portion of a stacked semiconductor package may be effectively radiated to the outside of the stacked semiconductor package
Implementation Method 2
by disposing a heating element that may generate a relatively large amount of heat and a member for heat dissipation at a second region of the first semiconductor package... the heat generated from the semiconductor chip may be effectively dissipated to the outside
Data Source
AI summary
A stacked semiconductor package includes: a first semiconductor package that includes a first region and a second region and includes a semiconductor chip including a first element at the first region and a second element at the second region; a second semiconductor package on the first region of the first semiconductor package; and a member for heat dissipation at the second region of the first semiconductor package and overlapping at least a portion of the second element in a vertical direction perpendicular to an in-plane direction of the first semiconductor package.