Semiconductor Package Vertical Interconnects Without Interposers

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Solution Overview

Problem

As the semiconductor industry continues to increase integration density by reducing minimum feature sizes, connecting integrated circuit dies through interposers alone becomes increasingly challenging due to the limitations of interposer technology in supporting high-density connections.

Innovation Solution

The integration of vertical interconnect features within the seal region of integrated circuit dies allows for direct connection between stacked dies without the need for interposers, utilizing edge interconnect features and vertical conductive features to facilitate signal and power transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If interposers are used to connect integrated circuit dies, then input/output communication is enabled, but routing density is limited and manufacturing complexity increases

Engineering Contradiction:
Improverouting densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the interposer layer from the packaging structure. By removing this intermediate component, the invention enables direct bonding between integrated circuit dies, thereby increasing routing density while reducing manufacturing complexity and the number of processing steps required

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions previously performed by separate components (interposer for routing and bonding for connection) into a single direct bonding interface. This integration allows signal routing and mechanical connection to occur simultaneously at the die-bonding interface, eliminating the need for redistribution layers on an interposer substrate

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If interposer layers are used for connecting dies, then signal transmission is achieved, but manufacturing costs increase due to additional layers and processes

Engineering Contradiction:
Improvesignal transmissionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention removes the interposer layer and associated redistribution processes from the manufacturing workflow. Direct die-to-die bonding eliminates the need for separate interposer fabrication, alignment, and bonding steps, thereby reducing manufacturing costs while maintaining signal transmission integrity through direct conductive pathways

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If traditional interposer-based connections are used, then die stacking is enabled, but power transfer efficiency is reduced due to additional interposer layers

Engineering Contradiction:
Improvedie stacking capabilityVSAvoidpower transfer efficiency
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

By eliminating the interposer layer, the invention creates direct electrical pathways for power transfer between stacked dies. This removal of intermediate layers reduces resistive losses and improves power transfer efficiency while maintaining the ability to stack multiple dies vertically through direct bonding interfaces

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250167126A1Semiconductor packages and methods for forming the same
Publication Date: 2025.05.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250167126A1 patent drawing
  • US20250167126A1 patent drawing
  • US20250167126A1 patent drawing

AI summary

Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.