Semiconductor Package Vertical Conductive Path Design

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Solution Overview

Problem

Existing semiconductor packages face challenges in efficiently connecting passive and electronic components to enhance transmission speed, as traditional configurations often result in longer conductive paths leading to higher impedance loss and slower signal transmission.

Innovation Solution

A semiconductor package design featuring a PoP (Package-On-Package) structure with a conductive component between two substrates, allowing the passive and electronic components to be disposed within an interval, connected via a conductive path through outermost conductive layers, reducing the length of the conductive path and increasing transmission speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional configurations are used to connect passive and electronic components, then the components can be connected, but the conductive path becomes longer leading to higher impedance loss and slower signal transmission

Engineering Contradiction:
Improvesignal transmission speedVSAvoidimpedance loss
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent transitions from a planar connection layout to a three-dimensional stacked configuration. Passive components and electronic components are arranged in different vertical layers (first substrate and second substrate), allowing conductive paths to extend in the vertical dimension rather than traversing long horizontal distances. This dimensional change dramatically shortens the conductive path length, reducing impedance loss and enhancing signal transmission speed.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a Package-On-Package (PoP) structure where one substrate (containing passive components) is stacked on top of another substrate (containing electronic components). The conductive component is nested between these two substrates, creating a compact vertical integration. This nesting approach allows multiple functional layers to occupy the same horizontal footprint while maintaining short inter-layer connections, thereby reducing overall signal path length and impedance loss.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Speed

If the conductive path length is reduced to increase transmission speed, then signal transmission improves, but the structural complexity of the package increases

Engineering Contradiction:
Improvesignal transmission speedVSAvoidpackage structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the semiconductor package into distinct functional segments: a first substrate containing passive components, a second substrate containing electronic components, and conductive components positioned between them. This segmentation allows each layer to be independently optimized and manufactured, then assembled into the final stacked structure. By segmenting the package, the design achieves short conductive paths for high-speed transmission while maintaining modular complexity that simplifies manufacturing and assembly processes.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11728320B2Semiconductor package
Publication Date: 2023.08.15 MEDIATEK INC
  • US11728320B2 patent drawing
  • US11728320B2 patent drawing
  • US11728320B2 patent drawing

AI summary

A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.