3D Stackable Semiconductor Package with Vertical Conductive Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packages with fine-pitch leads face challenges such as increased footprint, costly trimming tools, lead bending, and complex surface-mounting processes, which are not efficiently addressed by existing technologies.
Innovation Solution
A three-dimensional stackable semiconductor package with a sacrificial metal base, featuring electrical contact pads and conductive plugs formed through an encapsulant, allowing for higher density packaging and electrical connectivity between layers, enabling packages to be stacked and reducing the need for extensive rework.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional plastic packages with perimeter leads are used to accommodate a large number of leads, then the number of external terminals increases, but the footprint of the package increases
Solution Approach 1:
The patent transitions from two-dimensional perimeter leads to three-dimensional vertical interconnections. Conductive plugs extend through the encapsulant from the bottom surface to the top surface, enabling electrical connections in the vertical dimension rather than only along the perimeter, thus increasing terminal count without expanding footprint.
2Quantity of substance
If pin pitch is decreased to accommodate more pins without increasing footprint, then the number of pins increases, but trimming costs increase and leads are prone to bending
Solution Approach 1:
The patent extracts the trimming operation from the manufacturing process by eliminating protruding leads that require trimming. The conductive plugs are formed integrally within the encapsulant, removing the need for post-molding trimming operations and associated costs.
Solution Approach 2:
The patent replaces horizontal lead extensions with vertical conductive plugs. Instead of leads extending outward from the package perimeter requiring trimming, electrical connections are established through vertical plugs embedded in the encapsulant, eliminating the trimming problem.
3Area of stationary object
If conventional chip scale packages are used, then footprint is reduced, but specialized packaging materials and processes increase manufacturing costs
Solution Approach 1:
The patent creates a universal package structure that can accommodate various IC types (plastic, ceramic, chip scale) using standard molding and plating processes. The conductive plug architecture provides a common platform that eliminates the need for specialized μBGA or BCC manufacturing processes, reducing costs while maintaining small footprint.
4Quantity of substance
If fine-pitch packages are used, then pin count increases, but surface-mounting becomes costly and complicated due to critical alignment requirements
Solution Approach 1:
The patent replaces horizontal lead alignment requirements with vertical conductive plug connections. The top surface of the package provides a flat mounting interface with conductive plugs extending vertically, simplifying surface-mounting alignment compared to fine-pitch peripheral leads that require precise horizontal positioning.
Data Source
AI summary
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.