Semiconductor Package Vertical Stacking With Through-Electrodes
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Solution Overview
Problem
Semiconductor chip stacks with multiple layers and excessive thickness pose challenges in mounting on substrates during manufacturing, particularly in forming fine-pitch redistribution circuits due to thickness-related undulations, which restricts the formation of efficient thermal and electrical connections.
Innovation Solution
A semiconductor package design featuring a chip structure with multiple semiconductor chips stacked vertically and connected through through-electrodes, mounted on a separately manufactured substrate with a redistribution layer and encapsulants, allowing for a flip-chip configuration and fine-pitch redistribution circuits, enhancing yield and thermal/electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked with several layers to achieve miniaturization, then integration density is improved, but thickness increases making mounting difficult
Solution Approach 1:
The chip stack is divided into multiple semiconductor chips (first semiconductor chip, second semiconductor chip, etc.) that are stacked vertically and connected through through-electrodes. This segmentation allows each chip to be manufactured separately with standard processes while achieving high integration density when assembled, resolving the contradiction between quantity and manufacturability.
Solution Approach 2:
The patent transitions from lateral substrate connections to vertical stacking through through-electrodes, utilizing the third dimension (height) for interconnections. This dimensional change enables higher integration density without increasing planar footprint, while the substrate provides a stable mounting platform that accommodates the vertical structure.
2Quantity of substance
If chip stack thickness is increased to accommodate more layers, then integration density is improved, but formation of fine-pitch redistribution circuits becomes difficult due to undulations
Solution Approach 1:
The substrate with redistribution layer is prepared in advance before the chip stack is mounted. The redistribution layer patterns are formed on the substrate prior to chip assembly, allowing fine-pitch circuits to be created on a stable, flat surface. This preliminary action eliminates the problem of forming precise circuits on thick, undulating chip stacks.
Solution Approach 2:
The substrate acts as an intermediary platform between the chip stack and the external environment. It provides a flat mounting surface with pre-formed redistribution circuits, mediating the connection between the vertical chip stack and lateral circuit traces, thereby enabling fine-pitch routing without requiring precise circuit formation on the thick chip stack itself.
3Ease of manufacture
If traditional mounting methods are used for thick chip stacks, then manufacturing simplicity is maintained, but thermal and electrical connection efficiency is restricted
Solution Approach 1:
The patent implements vertical stacking with through-electrodes that extend through the entire chip stack, enabling direct electrical connections from the top chip to the substrate in a single vertical path. This three-dimensional interconnection approach improves electrical and thermal efficiency compared to traditional lateral routing, while the flip-chip mounting method maintains manufacturing simplicity through established processes.
Solution Approach 2:
The patent replaces traditional wire bonding or lateral trace connections with direct vertical electrical connections through through-electrodes and connection bumps. This substitution of the connection mechanism reduces connection length and impedance, improving electrical and thermal performance while maintaining ease of manufacture through automated pick-and-place mounting.
Data Source
AI summary
A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.