Semiconductor Package Routing with Encapsulated Vertical Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable and compact packaging solutions due to the limitations of existing integrated fan-out packages, which struggle with routing capability and reliability as feature sizes decrease, necessitating innovative manufacturing methods for efficient semiconductor package production.
Innovation Solution
A wafer-level packaging method involving a carrier with a debond layer and buffer layer, where a redistribution structure with polymer dielectric and metallization layers is formed, and semiconductor dies are attached with through vias and encapsulated, followed by planarization and additional redistribution sublayers, eliminating the need for a seed layer between metallization and conductive vias to enhance adhesion and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated fan-out packages are used to achieve compactness, then area usage is reduced, but routing capability and reliability deteriorate
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by forming conductive vias through the encapsulant material. This allows electrical connections to be established in the vertical dimension rather than relying solely on horizontal routing, thereby improving routing capability while maintaining compact package area.
Solution Approach 2:
The patent implements a multi-layered structure where redistribution layers, conductive vias, and encapsulant materials are nested within each other. The conductive vias are embedded within the encapsulant, and redistribution layers are positioned at different heights, creating a nested configuration that maximizes routing density in a compact volume.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing complexity and difficulty increase
Solution Approach 1:
The manufacturing process is divided into distinct sequential steps: forming the encapsulant material, creating conductive vias through the encapsulant, depositing redistribution layers, and forming additional conductive structures. This segmentation allows each step to be optimized independently and simplifies the overall manufacturing process despite the high integration density achieved.
3Ease of manufacture
If conventional packaging methods are used, then manufacturing process is simpler, but adhesion and structural integrity are insufficient
Solution Approach 1:
The patent employs composite material structures combining the encapsulant material with conductive vias and redistribution layers. The encapsulant serves as both a structural matrix and an adhesive medium, while the conductive materials are integrated within this matrix, creating a composite structure with enhanced adhesion and structural integrity compared to conventional packaging methods.
Data Source
AI summary
A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.