Multi-Chip Semiconductor Package With Vertical Wire Routing
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Solution Overview
Problem
In multi-chip packages, the need for vertical space for bonding wires increases the package size and height, making it difficult to reduce the package footprint while maintaining effective electrical connections.
Innovation Solution
A semiconductor package design that includes a package substrate, an encapsulation structure with vertically extending conductive wires, and conductive bumps between the substrate and the encapsulation structure, eliminating the need for an outer area around the semiconductor chips and reducing the package size and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires are used to electrically connect semiconductor chips to package substrate, then electrical connection is achieved, but vertical space and outer area are required increasing package size
Solution Approach 1:
The patent transitions from horizontal bonding wire routing to vertical conductive wire routing through the encapsulation structure. Conductive wires extend vertically from the package substrate through the encapsulation structure to reach chip pads, eliminating the need for horizontal loop heights and outer area extensions, thus reducing package volume while maintaining electrical connectivity
Solution Approach 2:
The conductive wires are nested within the encapsulation structure, with wires embedded in the encapsulant material extending from the substrate through the encapsulation body to the chips. This nesting eliminates the need for external wire routing space, allowing the package to be compact while maintaining all necessary electrical connections
2Reliability
If bonding wires extend outward from semiconductor chip, then electrical connection is established, but outer area around chip is required
Solution Approach 1:
The patent changes the routing dimension from horizontal (bonding wires extending outward) to vertical (conductive wires extending through encapsulation). Conductive wires pass vertically through the encapsulation structure directly above the chip area, eliminating the need for outer area extensions and reducing package footprint
3Reliability
If vertical space is provided for bonding wire loop heights, then bonding connection is enabled, but package height increases
Solution Approach 1:
Conductive wires are nested within the encapsulation structure, with wire loop portions contained inside the encapsulant body. This nesting allows the wires to achieve necessary mechanical strength and electrical connection without requiring external vertical space for loop heights, thereby reducing overall package height
4Volume of stationary object
If conductive wires extend vertically without outer area, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
Conductive wires are attached to the package substrate and encapsulation structure in advance during the encapsulation process, before final chip mounting. Wire bonding or attachment is performed while the encapsulation structure is being formed, integrating wire placement into the encapsulation manufacturing flow and avoiding separate complex wire routing steps
Data Source
AI summary
A semiconductor package includes a package substrate, an encapsulation structure stacked on the package substrate, a plurality of conductive bumps disposed between the package substrate and the encapsulation structure, and an adhesive layer attaching the package substrate and the encapsulation structure to each other. The encapsulation structure includes a sealing member having an upper surface and a lower surface opposite to each other, a plurality of semiconductor chips sequentially arranged in the sealing member such that a front surface on which chip pads are formed faces the package substrate, and conductive wires extending from a lower surface of the sealing member to the chip pads of the plurality of semiconductor chips. The plurality of conductive bumps are disposed between the conductive wires and substrate pads of the package substrate.