Semiconductor Package Via Hole Non-Uniform Spacing
Solution Overview
Problem
As semiconductor packages become smaller, the decreasing pitch between connecting via holes leads to overflow and short circuits between adjacent conductors due to the filling of internal spaces by connecting conductors, causing electrical connectivity issues.
Innovation Solution
The design incorporates connecting via holes with non-uniform planar distances between the exposed conductors and their entrances, and varying shapes and positions to create a buffer space, preventing conductor overflow and short circuits by ensuring a sufficient gap between adjacent conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pitch between connecting via holes is decreased to reduce package size, then compactness is improved, but short circuit between adjacent connecting conductors occurs due to overflow
Solution Approach 1:
The patent applies local quality by creating non-uniform planar distances between the exposed connecting conductors and the entrances of connecting via holes. Specifically, the distance varies at different locations around the via hole entrance, with larger distances positioned adjacent to neighboring via holes. This localized variation in spacing provides enhanced buffer spaces precisely where short circuit risks are highest, while maintaining tighter spacing in other areas to minimize overall package size.
Solution Approach 2:
The patent employs asymmetry by deliberately designing the connecting via holes with non-uniform characteristics. The planar distance from the exposed conductor to the via hole entrance is intentionally made asymmetric, with different distances measured at different angular positions around the via hole. This asymmetric configuration ensures that buffer spaces are strategically positioned to prevent short circuits between adjacent conductors, rather than using a uniform symmetric pattern that would require larger overall spacing.
2Reliability
If connecting conductors are filled into connecting via holes to establish electrical connection, then electrical connectivity is improved, but overflow occurs causing short circuits between adjacent conductors
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the connecting via holes with non-uniform planar distances to the exposed conductors before the conductors are filled in. The larger distances are strategically positioned at locations where adjacent via holes are closest, creating preventive buffer spaces that counteract the potential overflow effect. This preliminary design prevents short circuits before they can occur, rather than attempting to correct them after the fact.
Solution Approach 2:
The patent implements beforehand cushioning by creating extra buffer spaces in the form of non-uniform planar distances between the exposed conductors and via hole entrances. These cushioning spaces are positioned in advance at critical locations adjacent to neighboring via holes, providing a safety margin that absorbs the overflow of conducting material during the filling process. This cushioning effect prevents the harmful short circuit condition while maintaining effective electrical connection.
Data Source
AI summary
A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.