Semiconductor Package Via Hole Width Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in miniaturization, as high-resolution lithography is hindered by the non-smooth top surface of embedded semiconductor devices, limiting via hole width and pad pitch, and resulting in high manufacturing costs and low yield due to failures in redistribution layer formation.
Innovation Solution
A semiconductor package design featuring an encapsulation layer, dielectric layer with via holes, and embedded patterned conductive layers that allow for high-resolution techniques to reduce via hole width and pad pitch, improving yield and reducing manufacturing costs by integrating redistribution layers and conductive members within the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-resolution lithography is used to reduce via hole width and pad pitch, then manufacturing precision and productivity are improved, but the non-smooth top surface of embedded semiconductor devices prevents effective lithography application
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the embedded semiconductor device before applying the lithography process. This planarization layer creates a smooth surface in advance, enabling high-resolution lithography to be effectively applied despite the underlying non-smooth device topography. The sequence of operations ensures that surface irregularities are addressed before the critical patterning step.
2Reliability
If separate packaging, board manufacturing, and assembly processes are performed, then device reliability is maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges previously separate packaging, board manufacturing, and assembly processes into an integrated manufacturing flow. The semiconductor device is embedded directly into the substrate during substrate fabrication, and redistribution layers are formed in the same manufacturing sequence. This consolidation maintains device reliability through controlled processes while reducing overall manufacturing complexity and cost by eliminating multiple discrete process steps.
Data Source
AI summary
The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.