Semiconductor Package Through-Via Layout to Minimize Plating Dimples

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Solution Overview

Problem

Conventional large-area vias in semiconductor packages face challenges with dimple formation during plating, leading to increased plating processes and reduced product yield due to the difficulty in filling large-diameter via holes with metal materials, which affects the reliability and heat dissipation characteristics of printed circuit boards.

Innovation Solution

The semiconductor package incorporates a structure with multiple sub-vias arranged in a bar shape, where the width of the sub-vias in the first direction is greater than in the second direction, minimizing dimple formation by reducing the number of plating processes and maintaining consistent plating speed across different via groups, thereby improving heat dissipation and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a large-diameter via hole is filled with metal material to create a large-area via, then heat dissipation characteristics and shielding characteristics are improved, but it becomes difficult to fill the via hole completely, resulting in dimple formation and reduced reliability

Engineering Contradiction:

Improveheat dissipation characteristicsVSAvoidvia hole filling completeness

Core Design Contradiction:

TemperatureVSManufacturing precision

Solution Approach 1:

The large-area via is divided into multiple sub-vias arranged in an array pattern. Each sub-via has a smaller diameter that can be completely filled with metal material through plating processes, eliminating the dimple formation issue while collectively providing the required large effective area for heat dissipation and shielding functions.

Inventive Principle:

Principle #1Segmentation

2Temperature

If the width of the via in the first direction is increased to improve heat dissipation, then heat dissipation characteristics are improved, but the via requires more plating processes and creates larger dimples

Engineering Contradiction:

Improveheat dissipation characteristicsVSAvoidnumber of plating processes

Core Design Contradiction:

TemperatureVSProductivity

Solution Approach 1:

The via structure is segmented into multiple sub-vias with controlled dimensions. By arranging multiple smaller sub-vias in an array rather than using one large via, the effective heat dissipation area is increased while each individual sub-via can be plated in fewer processes with smaller dimples.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of increasing the width in one direction which exacerbates dimple formation, the solution distributes the heat dissipation function across multiple dimensions by arranging sub-vias in an array pattern, achieving large effective area through spatial distribution rather than single-direction expansion.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Temperature

If conventional large-area vias are used, then heat dissipation characteristics are improved, but dimple formation affects via hole processing during additional lamination and reduces reliability

Engineering Contradiction:

Improveheat dissipation characteristicsVSAvoidprinted circuit board reliability

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

The large-area via structure is segmented into multiple small sub-vias that can be completely filled with metal material. This eliminates the dimple formation problem that compromises via hole processing during lamination, thereby improving the overall reliability of the printed circuit board while maintaining the heat dissipation function.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of plating processes, minimizes dimple size, and maintains plating flatness, enhancing the reliability and heat dissipation characteristics of the circuit board by dividing vias into groups with varying intervals, thus improving overall manufacturing efficiency and product yield.

Implementation Method 1

improving heat dissipation characteristics

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

a first through electrode part passing through the first insulating layer

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

conventional large-area via includes a dimple region concavely recessed toward an inner direction of the via hole on one surface

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20240234281A9Semiconductor package

Publication Date: 2024.07.11 LG INNOTEK CO LTD

AI summary

A semiconductor package according to an embodiment includes a first insulating layer; and a first through electrode part passing through the first insulating layer and having a shape elongated in a first direction; wherein the first through electrode part includes a plurality of first through electrodes spaced apart from each other in a second direction perpendicular to the first direction and a thickness direction; wherein at least one of the plurality of first through electrodes includes a first sub through electrode and a second sub through electrode spaced apart from each other in the first direction; and wherein at least one of the first sub through electrode and the second sub through electrode has a width in the first direction greater than a width in the second direction.