Semiconductor Package Via Layout for Compressive Stress Relief
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Solution Overview
Problem
Semiconductor packages face reliability issues due to compressive stress caused by vertically aligned core vias, lower vias, and under bump vias, leading to potential cracks and reduced durability.
Innovation Solution
The semiconductor package design includes a core via, a lower via, and an under bump via, where at least one of these vias are spaced apart in a plan view, dispersing external forces and reducing compressive stress, thereby preventing cracks and enhancing reliability and durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If core via, lower via, and under bump via are vertically aligned, then manufacturing precision is improved, but compressive stress concentrates and reliability deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the via holes in different layers. Specifically, the under bump via is positioned offset from the core via and lower via in the plan view, creating an asymmetric arrangement that prevents vertical alignment. This asymmetric positioning disperses compressive stress away from concentrated points, thereby improving package reliability while maintaining acceptable manufacturing precision through controlled offset distances.
2Reliability
If vias are spaced apart in plan view, then compressive stress is reduced and reliability is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent applies parameter changes by optimizing the spacing distance between misaligned vias. The offset distance is carefully controlled within specific ranges to achieve sufficient stress dispersion while remaining within manufacturing capabilities. This parameter optimization ensures that the via holes are spaced apart enough to reduce compressive stress concentration, yet close enough to maintain acceptable positioning precision through standard manufacturing processes.
Data Source
AI summary
A semiconductor package may include a lower redistribution layer including a lower wiring and a lower via, an embedded region on the lower redistribution layer, a core layer on the lower redistribution layer and including a core via, and an under bump structure including an under bump pad on a lower surface of the lower redistribution layer and an under bump via connecting the lower wiring and the under bump pad, the under bump pad may overlap the under bump via, the lower via, and the core via in a plan view, and the under bump via may be spaced apart from at least one of the lower via and the core via in the plan view.