Semiconductor Package Via Structure for Fine Redistribution Patterns
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization and micropatterns while maintaining high functionality and reliability, particularly in fan-out packages where electrical connections are redistributed.
Innovation Solution
A semiconductor package design incorporating a first redistribution structure with a photosensitive insulating material and a dual seed layer via structure, which includes a first via with a titanium and copper seed layer, and a conductive layer to reduce surface roughness and enhance micropattern formation, along with a method of fabricating this structure using a photoresist process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional insulating materials and single seed layer via structures are used, then manufacturing process is simpler, but surface roughness is higher and micropattern formation is poor
Solution Approach 1:
The via structure is segmented into multiple functional layers: a first seed layer (e.g., titanium) for adhesion and a second seed layer (e.g., copper) for conductivity. This segmentation allows each layer to optimize its specific function, resulting in reduced surface roughness and improved micropattern formation while managing the complexity through modular design
Solution Approach 2:
The patent employs composite material structures in multiple aspects: the insulating layer combines photosensitive material with filler particles, the via structure combines different metal seed layers, and the redistribution layers use composite conductor-insulator-conductor stacks. These composite structures enable simultaneous achievement of low surface roughness, good adhesion, and electrical functionality
2Reliability
If photosensitive insulating material with filler is used, then electrical insulation is improved, but micropattern formation and surface roughness are worsened
Solution Approach 1:
The patent applies local quality by using a photosensitive insulating material formulation where filler content and distribution are optimized for specific regions. The insulating layer maintains high electrical insulation properties while the photosensitive component enables precise micropattern formation through photolithography, achieving both reliability and manufacturing precision in different aspects of the same material layer
Solution Approach 2:
The patent changes material parameters by selecting specific filler types, sizes, and concentrations in the photosensitive insulating material. By optimizing these parameters, the material achieves both high electrical insulation performance and good flow characteristics for micropattern formation, resolving the contradiction between reliability and manufacturing precision
3Volume of moving object
If component size is reduced for miniaturization, then package density is improved, but manufacturing precision and reliability are worsened
Solution Approach 1:
The patent transitions from planar miniaturization to three-dimensional vertical stacking with multiple redistribution layers and via structures. This dimensional change allows continued package density improvement through vertical integration while maintaining manufacturing precision through standardized via and layer thicknesses that are less sensitive to lateral dimension reductions
Solution Approach 2:
The patent incorporates preliminary actions in the manufacturing process, such as forming seed layers before via holes, applying protective films before redistribution layer formation, and using carrier substrates during fabrication. These preliminary actions ensure manufacturing precision is maintained even as component sizes are reduced for miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design allows for reduced component size and improved micropatterns with enhanced electrical connectivity and reliability, facilitating thinner and more efficient semiconductor packages.
Implementation Method 1
the first sealing layer includes a photosensitive insulating material integrally covering the second surface of the first semiconductor chip and a sidewall of the first seed layer
Data Source
AI summary
Provided is a semiconductor package. The semiconductor package may include a first redistribution structure, a first semiconductor chip including a first surface and a second surface, the first surface being disposed to face the first redistribution structure, a second redistribution structure disposed on the second surface of the first semiconductor chip and including a second insulating layer and a second redistribution layer, a first sealing layer disposed between the first and second redistribution structures and configured to cover the second surface of the first semiconductor chip, and a connection structure configured to connect the first and the second redistribution structures, wherein the second redistribution layer includes a first via and a second via on the first via, wherein the first via includes first and second seed layers, and a conductive layer on the second seed layer, and wherein the first sealing layer includes a photosensitive insulating material.