Semiconductor Package Layout Using Via-Plugs for Higher Integration
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Solution Overview
Problem
The challenge in the electronics industry is to achieve high integration and miniaturization of semiconductor packages while reducing manufacturing costs, as larger packages incur higher costs due to increased size.
Innovation Solution
The solution involves a semiconductor package design that includes via-plugs passing through the substrate, electrically connected to pads, allowing for miniaturization and increased area for additional elements or devices, enhancing design flexibility by facilitating the integration of surface mount devices and conductive elements through solder connections and bonding wires, and encapsulating components with a molding compound for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high integration is achieved to increase system functionality, then system performance is improved, but manufacturing cost increases due to larger package size
Solution Approach 1:
The patent utilizes through-holes penetrating the substrate to create vertical electrical connections, transitioning from planar to three-dimensional routing. This allows multiple signal paths and device interconnections within the same footprint area, enabling high integration without increasing package size, thus maintaining cost-effectiveness while enhancing system functionality.
Solution Approach 2:
The patent embeds passive elements such as capacitors and inductors within the substrate structure itself, nesting these components inside the package rather than mounting them externally. This nested arrangement maximizes space utilization, allowing multiple functional elements to coexist in a compact configuration, thereby achieving high integration without proportionally increasing manufacturing cost.
2Volume of stationary object
If package size is reduced to achieve miniaturization, then manufacturing cost decreases, but available area for additional elements is reduced
Solution Approach 1:
By implementing through-holes that extend vertically through the substrate, the patent creates additional routing dimensions. This three-dimensional approach allows electrical connections to be made in the vertical direction rather than requiring extensive lateral space, enabling miniaturization while preserving functional area for additional elements.
Solution Approach 2:
The substrate is divided into multiple regions with through-holes strategically positioned to provide electrical interconnection between different areas. This segmentation allows independent placement of active and passive elements in optimized locations, maximizing the utilization of available area within the reduced package footprint.
3Adaptability or versatility
If through-holes are formed through the substrate to increase integration density, then design flexibility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The through-holes serve multiple functions simultaneously: they provide electrical interconnection between different substrate layers, act as mounting structures for passive elements, and enable thermal management pathways. This multi-functionality reduces the need for separate specialized structures, thereby enhancing design flexibility without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent combines several functions into the through-hole structure itself, merging electrical connection, mechanical support, and thermal conduction pathways into a single integrated feature. This consolidation simplifies the overall manufacturing process by reducing the number of separate operations required, thereby maintaining design flexibility while controlling manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design facilitates miniaturization of IC packages, increases area for additional elements, and enhances design flexibility, thereby reducing manufacturing costs and improving integration density.
Implementation Method 1
via-plugs passing through the substrate and electrically connected to pads
Implementation Method 2
A semiconductor chip is mounted on the substrate and soldered to a corresponding pad
Implementation Method 3
a bond wire connecting the semiconductor element to an external lead
Implementation Method 4
encapsulating components with a molding compound for protection
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
A semiconductor package is provided. The semiconductor package includes a substrate(118), a first pad(112), a second pad(114), a first conductive element(142), a surface mount device(120), a first bonding wire (140) and a molding compound layer(166). The first pad,the second pad, and the first conductive element are formed on the substrate. The surface mount device is mounted on the first pad and the second pad. The first bonding wire electrically connects the first conductive element and the first pad. The molding compound layer encapsulates the substrate, the first pad, the second pad, the first conductive element, the bonding wire and the surface mount device.