Semiconductor Package Via Structure for Stable Power Routing
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Solution Overview
Problem
The increasing demand for compact, lightweight, and high-performance semiconductor packages poses challenges in ensuring reliable power supply and structural integrity, particularly due to the downsizing and weight reduction of semiconductor packages.
Innovation Solution
A method of manufacturing a semiconductor package involves attaching a film structure with an insulating layer and seed layers to the active surface of a semiconductor chip, forming via holes, and performing a descum process followed by the deposition of additional seed layers and conductive materials to create reliable conductive vias and patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If semiconductor packages are downsized and weight reduced to meet compact device requirements, then the size and weight of semiconductor packages decrease, but the reliability and stability of power supply deteriorate
Solution Approach 1:
The patent transitions from planar power distribution to a three-dimensional vertical architecture by stacking multiple semiconductor chips and redistribution layers in the thickness direction. This vertical integration maintains compact footprint while providing redundant power supply paths through multiple layers, thereby improving reliability without increasing package weight.
Solution Approach 2:
The patent employs composite redistribution layers combining conductive materials (copper, aluminum) with insulating materials (dielectric layers) to create multi-functional structures. These composite layers provide both electrical connectivity for power supply and mechanical support for structural integrity, ensuring reliable power distribution in downsized packages.
2Power
If the capacity and power handling of semiconductor packages are increased to meet performance demands, then the power consumption and heat generation increase, but the thermal management and reliability become more challenging
Solution Approach 1:
The patent divides the power distribution function across multiple separate redistribution layers and conductive vias stacked vertically. This segmentation distributes heat generation across multiple interfaces and pathways, preventing localized thermal hotspots and facilitating heat dissipation through the package structure.
Solution Approach 2:
The patent introduces intermediate thermal management structures including thermal interface materials between chips and heat dissipation pathways through the substrate. These intermediary elements facilitate efficient heat transfer from high-power regions to external heat sinks, managing temperature rise in high-power applications.
3Reliability
If complex redistribution structures are designed to improve power supply stability in compact packages, then the manufacturing precision and process complexity increase
Solution Approach 1:
The patent performs preliminary planarization and surface preparation of chip bonding surfaces before stacking. This preliminary action ensures flat, uniform surfaces that facilitate precise alignment and formation of via holes in subsequent processing steps, reducing manufacturing complexity despite the multi-layer structure.
Solution Approach 2:
The patent replaces complex mechanical alignment systems with self-aligned fabrication processes where via holes are automatically positioned based on predefined patterns in the redistribution layers. This substitution of alignment methodology reduces the need for high-precision mechanical positioning equipment and simplifies manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of semiconductor packages by ensuring stable power supply and structural integrity, while also accommodating the size and performance requirements of modern semiconductor packages.
Implementation Method 1
forming a conductive via by filling a space defined by the via hole with a conductive material and forming a conductive pattern by filling a space defined by the photoresist pattern with the conductive material
Data Source
AI summary
A method of manufacturing a semiconductor package with a semiconductor chip including an active surface and an inactive surface opposite to the active surface is presented. The method includes attaching, to the active surface, a film structure including an insulating layer and a first seed layer contacting the insulating layer. A via hole is formed by penetrating the insulating layer and the first seed layer followed by a descumming the insulating layer and the first seed layer in which the via hole is formed. A second seed layer is formed on the insulating layer and on the first seed layer on which the descum process was performed. A photoresist pattern on the second seed layer enables forming a conductive via by filling both a space defined by the via hole with a conductive material and by filling a space defined by the photoresist pattern with the conductive material.