Semiconductor Package Interconnection Structure for Fine Via Reliability
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reliable and durable electrical connections between semiconductor chips and printed circuit boards due to limitations in manufacturing processes, particularly in forming fine interconnection structures that maintain structural integrity and prevent defects.
Innovation Solution
A method involving the formation of a photoimageable dielectric layer with a hard mask layer, followed by a dry etching process to create via holes and trenches, and subsequent metal layer deposition to form a wiring pattern, ensuring precise alignment and connection of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used to form interconnection structures, then the structure can be formed with basic functionality, but the reliability and durability of electrical connections deteriorate due to inability to form fine interconnection structures with structural integrity
Solution Approach 1:
The patent segments the interconnection structure formation into multiple distinct layers: a first conductive layer formed in via holes to provide vertical electrical connection, and a second conductive layer formed on the first conductive layer to provide horizontal wiring. This segmentation allows each layer to be optimized independently for its specific function, improving overall reliability while maintaining manufacturing precision through controlled formation processes for each segment.
Solution Approach 2:
The patent applies different materials and formation methods to different parts of the interconnection structure. The via holes are filled with a first conductive material optimized for vertical connection reliability, while the wiring layer uses a second conductive material optimized for horizontal signal transmission. This local quality differentiation ensures that each region of the interconnection structure has the specific properties needed for its function, thereby improving overall reliability without compromising manufacturing precision.
2Reliability
If fine interconnection structures are formed to improve electrical connection reliability, then connection quality improves, but manufacturing complexity increases making it difficult to maintain structural integrity
Solution Approach 1:
The patent divides the complex interconnection formation process into segmented steps: forming via holes through the dielectric layer, filling them with first conductive material, then forming the second conductive layer on top. This segmentation reduces manufacturing complexity by making each step manageable and controllable, while still achieving fine interconnection structures with high reliability. Each segment can be processed independently with appropriate process control.
Solution Approach 2:
The patent performs preliminary actions by first forming the via holes and filling them with conductive material before forming the wiring layer. This preliminary preparation ensures that the vertical connection paths are established and structurally intact before the horizontal wiring is added, reducing the overall manufacturing complexity by preparing the structure in a logical sequence rather than attempting to form all features simultaneously.
3Ease of manufacture
If conventional via hole formation processes are used, then the process can be completed with standard equipment, but defects occur reducing the durability of electrical connections
Solution Approach 1:
The patent applies local quality by filling only the via hole regions with conductive material while leaving the surrounding dielectric layer intact. This localized filling approach, achieved through controlled deposition processes, maintains ease of manufacture by using standard semiconductor fabrication techniques while improving reliability by ensuring complete and defect-free filling of the via holes. The conductive material is deposited conformally to ensure uniform filling without voids or defects.
Solution Approach 2:
The patent performs preliminary via hole formation and filling before forming the wiring layer. This preliminary action allows standard via formation equipment and processes to be used, maintaining ease of manufacture. The via holes are completely formed and filled with conductive material first, ensuring structural integrity and durability of the vertical connections before proceeding to the wiring formation step, thereby eliminating defects that would compromise connection durability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and durability of semiconductor packages by improving the formation of fine interconnection structures, reducing defects, and increasing the reliability of electrical connections.
Implementation Method 1
The etching the photoimageable dielectric layer and the hard mask layer may include placing a mask pattern including a first opening vertically overlapping the preliminary via hole and a second opening spaced apart from the first opening on the hard mask layer
Data Source
AI summary
A method for manufacturing a semiconductor package may include: forming a photoimageable dielectric layer on a substrate including a pad; forming a preliminary via hole in the photoimageable dielectric layer to expose the pad; forming a hard mask layer on the photoimageable dielectric layer and the pad; etching the photoimageable dielectric layer and the hard mask layer to form a via hole, a first hole, and a trench; forming a metal layer on the photoimageable dielectric layer connected to the pad; planarizing the metal layer to form a wiring pattern; and placing a semiconductor chip electrically connected to the wiring pattern. The first hole may be disposed on the via hole and connected thereto, and a diameter of the first hole may be larger than a diameter of the via hole.