Semiconductor Package Antenna Module Via Shielding
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Solution Overview
Problem
In high-performance electronic devices, such as those using mm-Wave and 5G antenna modules, there is a need to reduce mutual interference between components while achieving miniaturization, which existing semiconductor packages struggle to address due to limitations in electromagnetic wave shielding and spatial constraints.
Innovation Solution
A semiconductor package with a through via structure that enhances electrical shielding by using a wiring chip with penetrating vias to connect between the antenna substrate and semiconductor chips, along with a metal layer on the through-holes for improved electromagnetic wave shielding and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If electromagnetic wave shielding structures are added to reduce mutual interference, then shielding characteristics improve, but device complexity increases
Solution Approach 1:
The patent combines the shielding function with the existing via structure by forming a conductive metal layer on the via holes. This integration merges the shielding function into the existing interconnection structure, eliminating the need for separate shielding components and reducing overall device complexity while maintaining effective EMI shielding.
Solution Approach 2:
The via holes serve multiple functions: they provide electrical interconnection between layers and simultaneously act as shielding structures when the metal layer is formed on them. This multi-functionality allows the same structural element to address both signal transmission and electromagnetic interference protection, simplifying the overall design.
2Volume of moving object
If miniaturization is pursued to reduce package size, then spatial constraints are reduced, but electromagnetic wave shielding becomes more difficult
Solution Approach 1:
The patent applies shielding selectively to specific via holes that carry high-frequency signals or high-speed data, rather than implementing universal shielding across all vias. This localized approach provides targeted EMI protection where it is most needed while minimizing the impact on package size and maintaining miniaturization benefits.
3Speed
If through vias are used for high frequency signal transmission, then signal connectivity is improved, but electromagnetic interference increases
Solution Approach 1:
The patent converts the via hole structure, which initially causes EMI, into a shielding element by forming a conductive metal layer on its surface. The same via structure that enables high-speed signal transmission now also provides electromagnetic shielding, transforming the source of interference into a protective element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces electromagnetic interference and allows for miniaturization of the semiconductor package, enhancing both electrical and thermal performance in high-frequency applications.
Implementation Method 1
it is necessary to have various electromagnetic wave shielding structures to realize excellent shielding characteristics against electromagnetic interference (EMI)
Implementation Method 2
along with a metal layer on the through-holes for improved electromagnetic wave shielding and heat dissipation
Data Source
AI summary
A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.