Semiconductor Package Via Shielding for EMI Reduction

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Solution Overview

Problem

In semiconductor packages and antenna modules, especially for mm-Wave and 5G communications, there is a need to reduce mutual interference and electromagnetic interference (EMI) while miniaturizing components, which existing technologies struggle to achieve effectively.

Innovation Solution

A semiconductor package design that includes a metal layer on the entire surface of a frame within the package, with a via penetrating through an insulating layer to enhance electrical shielding between the via and the semiconductor chip, and additional metal layers on the through-holes to provide comprehensive shielding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If components are miniaturized for high performance, then device size is reduced, but electromagnetic interference between components increases

Engineering Contradiction:
Improvecomponent sizeVSAvoidelectromagnetic interference
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

A via structure with conductive filling material is introduced as an intermediary shielding element between the antenna and semiconductor chip. The via includes a via hole penetrating the substrate, filled with conductive material, and optionally covered with a reflective film, creating a Faraday cage effect that blocks electromagnetic interference while allowing compact component integration

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The via structure is nested within the substrate, with the via hole penetrating through the substrate thickness. The conductive filling material is nested within the via hole, and the reflective film is nested on the via hole opening, creating a multi-layer nested shielding structure that maximizes EMI protection in a compact volume

Inventive Principle:
Principle #7Nested doll (Nesting)

2Object-affected harmful factors

If shielding structures are added to reduce electromagnetic interference, then EMI protection is improved, but device complexity increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidstructure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The via structure serves multiple functions: it provides electrical connection between layers, acts as an electromagnetic shield through its conductive filling material, and can be integrated with existing substrate structures. This multi-functionality reduces the need for separate shielding components, thereby limiting complexity increase

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The via structure's shielding effectiveness is optimized by adjusting parameters such as the conductive filling material's conductivity, the via hole's dimensions and position, and the reflective film's properties. These parameter optimizations enhance EMI protection while maintaining a simple structural form that integrates easily with existing devices

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively eliminates mutual interference and enhances electromagnetic wave shielding, improving the performance and reliability of semiconductor packages and antenna modules by reducing EMI and allowing for more compact and efficient component integration.

Implementation Method 1

a via penetrating through an insulating layer to enhance electrical shielding between the via and the semiconductor chip, and additional metal layers on the through-holes to provide comprehensive shielding

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS10896884B2Semiconductor package and antenna module including the same
Publication Date: 2021.01.19 SAMSUNG ELECTRONICS CO LTD
  • US10896884B2 patent drawing
  • US10896884B2 patent drawing
  • US10896884B2 patent drawing

AI summary

A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.