Semiconductor Package Via and Encapsulant for Vertical Stacking
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving compact circuit density due to the increased size and thickness caused by the use of leadframes, and vertical stacking of components is limited without effective electrical coupling.
Innovation Solution
A semiconductor package design featuring a via partially covered by an encapsulant, which forms parallel surfaces and provides electrical coupling between the top and bottom surfaces, allowing for the stacking of components and potential embedding in a substrate, with conductive pads and traces for additional connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a leadframe is used for support during packaging, then structural support is provided, but package size and thickness increase
Solution Approach 1:
The patent removes the leadframe from the packaging structure entirely, replacing it with an encapsulant that provides both structural support and electrical insulation. This extraction of the leadframe eliminates the volume occupation while maintaining necessary structural functions through alternative means (encapsulant + substrate integration).
Solution Approach 2:
The patent merges the structural support function and electrical insulation function into a single encapsulant component, eliminating the need for separate leadframe structures. The encapsulant combines mechanical support with electrical properties, reducing overall package volume while maintaining functionality.
2Quantity of substance
If components are stacked vertically to increase circuit density, then effective circuit density increases, but electrical coupling between stacked components becomes limited
Solution Approach 1:
The patent introduces vias as intermediary conductive structures that penetrate through the encapsulant layer to establish reliable electrical coupling between vertically stacked components. These vias serve as mediators that bridge the electrical connection across multiple packaging layers, enabling vertical stacking while maintaining electrical reliability.
Solution Approach 2:
The patent transitions from planar electrical coupling to three-dimensional vertical coupling by implementing vias that extend through the encapsulant thickness. This dimensional change allows electrical connections to be established in the vertical direction, enabling effective stacking of multiple circuit components with reliable inter-layer coupling.
3Strength
If the encapsulant completely covers the via, then protection is provided, but electrical coupling through the encapsulant is blocked
Solution Approach 1:
The patent applies local quality by selectively exposing portions of the via at the top and/or bottom surfaces of the encapsulant while maintaining encapsulation of the via body. This localized exposure provides both protection (encapsulated portions) and electrical coupling (exposed portions), creating different functional zones within the same structure.
Data Source
AI summary
A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.