Semiconductor Package Via Structure for Heat Paths and EMI Shielding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in achieving efficient thermal radiation and improved electrical properties, particularly as semiconductor chip sizes decrease and diversified mount boards for various chip sizes are not readily available.
Innovation Solution
A semiconductor package design that includes a lower redistribution substrate, a module structure with interposer substrates and semiconductor chips, a connection substrate, a dielectric member, and an upper redistribution substrate, with vias penetrating through the dielectric member and molding layer to connect the semiconductor chips to the redistribution substrates, enhancing thermal radiation and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor chip size is reduced with high integration designs, then integration density is improved, but handling and testing difficulty increases
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary component that holds multiple semiconductor chips during manufacturing and testing processes. This carrier substrate serves as a mediator between the small semiconductor chips and handling equipment, enabling easy manipulation, transport, and testing of chips without directly handling the tiny chips themselves. The carrier substrate can be easily attached to testing equipment and then transferred to packaging equipment, streamlining the entire process.
2Adaptability or versatility
If fan-out panel level package is used to adapt board for various semiconductor chips, then versatility is improved, but area of redistribution lines increases
Solution Approach 1:
The patent transitions from planar redistribution lines on a single layer to a three-dimensional structure with multiple layers of redistribution substrates stacked vertically. The lower redistribution substrate and upper redistribution substrate are positioned at different heights, with connection substrates bridging between them. This vertical stacking approach reduces the horizontal area required for redistribution lines while maintaining the ability to connect to various chip sizes through the adaptable module structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design increases thermal radiation efficiency by using vias as heat paths and improves electrical properties by shielding electromagnetic interference, while accommodating semiconductor chips of various sizes through adaptable module structures.
Implementation Method 1
A first via may be in a first vertical hole that vertically penetrates the dielectric member and the molding layer. The first via may connect a wiring pattern of the upper redistribution substrate to a top surface of the first semiconductor chip.
Implementation Method 2
The module structure may include: an interposer substrate; a first semiconductor chip wire-bonded to the interposer substrate
Data Source
AI summary
A semiconductor package includes a lower redistribution substrate, a module structure on the lower redistribution substrate, a connection substrate on the lower redistribution substrate and at sides of the module structure, a dielectric member on the lower redistribution substrate between the connection substrate and the module structure, and an upper redistribution substrate on the dielectric member. The module structure includes an interposer substrate, a first semiconductor chip, and a molding layer. The molding layer and the dielectric member include different materials. A first via in a first vertical hole vertically penetrates the dielectric member and the molding layer. The first via connects a wiring pattern of the upper redistribution substrate to a top surface of the first semiconductor chip.