Semiconductor Package Multi-Layer Wiring via Vertical Vias
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to high-density wire bonding pads, which lead to difficulties in the wire bonding process and increased risk of short circuits, and limited wiring space that restricts circuit formation to a single plane.
Innovation Solution
A semiconductor package with a substrate featuring switching pads, conductive pads, and circuits between them, covered by an insulating layer and a conductive layer that extends to the switching and conductive pads, allowing for electrical connections via bonding wires, and an encapsulant to prevent short circuits and facilitate miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the density of wire bonding pads is increased to meet miniaturization requirements, then the package size is reduced, but the difficulty of wire bonding process increases and short circuit risk increases
Solution Approach 1:
The patent introduces a via structure that extends vertically through the substrate, transitioning the wiring from a planar two-dimensional arrangement to a three-dimensional multi-layer structure. This allows bonding pads to be distributed across multiple layers (first and second conductive layers separated by insulating layers), effectively increasing the available wiring space without increasing the package footprint, thus resolving the contradiction between miniaturization and wire bonding difficulty
Solution Approach 2:
The substrate is divided into multiple conductive layers separated by insulating layers, with via structures providing vertical connections between layers. This segmentation distributes the wire bonding pads across different layers, reducing the density requirement on any single layer and making the wire bonding process more manageable while maintaining miniaturization benefits
2Volume of moving object
If the density of wire bonding pads is increased to meet miniaturization requirements, then the package size is reduced, but the risk of short circuit between adjacent bonding wires increases
Solution Approach 1:
By introducing vertical via structures that connect different conductive layers, the patent separates adjacent bonding wires in the horizontal plane into different vertical layers. The insulating layers between conductive layers provide physical isolation, reducing the risk of short circuits between adjacent bonding wires while maintaining the miniaturized package size
Solution Approach 2:
The via structures and insulating layers act as intermediaries that provide controlled pathways for electrical connections while preventing unwanted short circuits. The insulating layers serve as mediators that physically separate adjacent conductive elements, reducing short circuit risk in the miniaturized structure
3Reliability
If the wire loop height is increased to prevent short circuits, then the reliability is improved, but the overall package height increases and miniaturization is hindered
Solution Approach 1:
Instead of increasing the wire loop height in the vertical direction, the patent distributes bonding pads across multiple horizontal layers connected by via structures. This allows short circuit prevention through layer separation while maintaining a compact overall package height, as the isolation is achieved through horizontal layering rather than vertical wire loop extension
4Ease of manufacture
If a single circuit layer is used in the substrate, then the manufacturing is simplified, but the wiring space is limited and circuit formation is restricted to a plane
Solution Approach 1:
The substrate is segmented into multiple conductive layers separated by insulating layers, with via structures providing vertical interconnections. This multi-layer segmentation dramatically increases wiring space flexibility and allows three-dimensional circuit formation while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes
Solution Approach 2:
The patent transitions from a single-planar circuit layer to a multi-layer three-dimensional circuit structure. The via structures enable vertical connections between layers, providing wiring space flexibility and circuit design adaptability while the layer-by-layer fabrication approach maintains manufacturing simplicity
Data Source
AI summary
A semiconductor package is disclosed, which includes: a substrate having a plurality of switching pads, a plurality of first conductive pads and a plurality of circuits formed between the switching pads and the first conductive pads; an insulating layer covering the circuits; a conductive layer formed on the insulating layer and extending to the switching pads and the first conductive pads; and a semiconductor element disposed on the substrate and electrically connected to the switching pads through a plurality of bonding wires. By electrically connecting the switching pads and the first conductive pads through the conductive layer, the invention dispenses with the conventional short bonding wires so as to prevent the conventional problem of short circuits caused by contact of the short bonding wires with other bonding wires.