Semiconductor Package Layout for High-Frequency Voltage Noise
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Solution Overview
Problem
Semiconductor packages with high-performance semiconductor chips face issues such as system malfunctioning and performance degradation due to voltage noise generated in high-frequency bands, which affects power integrity (PI) properties.
Innovation Solution
The semiconductor package includes a base substrate, a redistribution substrate with insulating and pattern layers, a semiconductor chip with specific bump structures and passive devices, and an encapsulant. This configuration reduces the connection path between the passive device and the semiconductor chip, enhancing power integrity by effectively removing voltage noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-performance semiconductor chip is embedded in a semiconductor package, then system performance is improved, but voltage noise is generated in high-frequency bands causing system malfunctioning and performance degradation
Solution Approach 1:
A passive device (capacitor) is introduced as an intermediary element between the semiconductor chip and the external circuit. This capacitor acts as a noise filter that absorbs and dissipates voltage noise generated by the high-performance semiconductor chip in high-frequency bands, preventing the noise from causing system malfunctioning while maintaining the chip's performance benefits
2Ease of manufacture
If a conventional packaging technique is used, then manufacturing cost is reduced, but power integrity properties deteriorate due to voltage noise
Solution Approach 1:
The passive device (capacitor) is merged with the semiconductor chip to form an integrated chip structure. This integration allows the noise filtering function to be incorporated into the chip itself without requiring separate packaging components or complex manufacturing processes, thereby maintaining ease of manufacture while improving power integrity properties by reducing voltage noise
3Reliability
If silicon interposers are used to improve power integrity, then voltage noise is reduced, but manufacturing cost increases significantly
Solution Approach 1:
The patent replaces expensive silicon interposers with a cost-effective alternative: a simple passive device (capacitor) that can be manufactured using standard semiconductor fabrication processes. This passive device achieves the same power integrity improvement by filtering voltage noise, but at a fraction of the cost of silicon interposers, making the solution economically viable for mass production
Data Source
AI summary
A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.