Semiconductor Package Voltage Reference Plane Nesting
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Solution Overview
Problem
Current semiconductor package fabrication techniques face form-factor constraints due to the integration of fully integrated voltage regulators (FIVR) and air core inductors, leading to enlarged package sizes and increased costs, which negatively impact device performance and power integrity.
Innovation Solution
A semiconductor package design that includes a voltage reference plane embedded within the footprint of the package die, providing electromagnetic shielding and allowing for the placement of components under the die, thereby reducing the air core inductor keep-out zone and increasing BGA I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIVR and ACI structures are integrated into the package substrate, then voltage regulation functionality is improved, but the package footprint and size are enlarged
Solution Approach 1:
The patent embeds the voltage reference plane within the die footprint area, nesting it inside the existing package structure rather than adding it externally. This allows the voltage regulation functionality to be integrated without increasing the overall package footprint, as the reference plane utilizes the space already occupied by the die.
Solution Approach 2:
The patent transitions from a two-dimensional layout where voltage regulation components are placed on the substrate surface to a three-dimensional structure by embedding the voltage reference plane within the substrate layers. This vertical integration allows voltage regulation functionality to be achieved without consuming additional horizontal footprint area.
2Object-affected harmful factors
If air core inductor keep-out zone is enlarged to ensure robust functionality, then electromagnetic interference is reduced, but BGA I/O density is limited
Solution Approach 1:
The voltage reference plane is nested within the die footprint, allowing passive components to be placed in the previously restricted keep-out zone. This nesting approach maintains electromagnetic shielding while recovering the BGA I/O area that was lost to the keep-out zone.
Solution Approach 2:
The patent creates localized electromagnetic shielding by embedding the voltage reference plane specifically in regions where it is most needed, rather than requiring a large universal keep-out zone. This allows BGA I/O to be placed in areas where electromagnetic interference is naturally shielded or minimal.
3Area of stationary object
If passive component count is reduced to accommodate FIVR/ACI integration, then package size is reduced, but device performance is affected
Solution Approach 1:
By nesting the voltage reference plane within the die footprint, the patent enables the placement of passive components in the recovered space without increasing overall package size. This maintains both the reduced package dimensions and the necessary component count for device performance.
Solution Approach 2:
The embedded voltage reference plane creates additional available space in the horizontal plane by utilizing vertical substrate layers. This allows passive components to be placed without increasing package footprint, maintaining both compact size and adequate component count for performance.
4Adaptability or versatility
If package size is enlarged to accommodate passive components, then continuous device bandwidth and I/O scaling is enabled, but form-factor requirements are negatively impacted
Solution Approach 1:
The embedded voltage reference plane recovers BGA I/O area within the existing package footprint, enabling continued I/O scaling without increasing package size. This nesting approach maintains form-factor requirements while supporting adaptability for bandwidth and I/O scaling.
Solution Approach 2:
By moving the voltage reference plane to a embedded three-dimensional configuration, the patent recovers horizontal footprint area that can be used for additional BGA I/O, enabling I/O scaling without increasing package dimensions and thus maintaining form-factor compliance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves miniaturization of the package form factor, improves power integrity, and enhances electromagnetic interference shielding, leading to increased BGA I/O density and reduced costs.
Implementation Method 1
A voltage reference plane may be disposed on the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the footprint of the die
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor package configured to provide for a disposition of one or more package components on a substrate within a footprint of a package die. In embodiments, the package may include a package substrate having a first side and a second side opposite the first side. An area of the first side of the package substrate within which a die is to be disposed may form a footprint of the die on the substrate. The package may further include a voltage reference plane coupled with the second side of the package substrate. At least a portion of the voltage reference plane may be disposed within the die footprint, to provide a reference voltage to components to be disposed within the footprint on the second side of the substrate, and to shield these components from electromagnetic interference. Other embodiments may be described and/or claimed.