Semiconductor Package Layout With On-Substrate Voltage Regulators
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high performance computing (HPC) and thermal management with better power integrity, particularly in large-scale AI training devices, due to issues with yield, thermal mechanical stress, and power integrity in current wafer-level packaging techniques.
Innovation Solution
The integration of redistribution layers with dense copper traces, voltage regulator modules, integrated stacked capacitors, liquid cooling channels, and thermal vias within a wafer-scale or panel-scale Si or glass substrate to enhance power integrity and thermal management, allowing for larger chip integration and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging techniques are used for large-scale AI training devices, then manufacturing efficiency is improved, but power integrity and thermal management performance deteriorate
Solution Approach 1:
The patent divides the wafer into multiple independent packaging units, each with its own voltage regulator module and power delivery network. This segmentation allows each unit to be optimized independently for power integrity while maintaining high manufacturing efficiency through wafer-level processing. The redistribution layers are configured to provide dedicated power paths for each packaging unit, preventing power integrity degradation.
Solution Approach 2:
The patent transitions from traditional planar power distribution to a three-dimensional power delivery network using multiple redistribution layers stacked vertically. This dimensional change enables shorter current paths and reduced inductance, improving power integrity while maintaining the manufacturing efficiency of wafer-level packaging. The vertical stacking of power and ground layers creates low-inductance power delivery paths.
2Productivity
If wafer-level packaging techniques are used for large-scale AI training devices, then manufacturing efficiency is improved, but thermal management performance deteriorates
Solution Approach 1:
The patent introduces thermal vias and heat dissipation structures as intermediary elements between the high-power chips and the substrate. These intermediaries conduct heat away from the chips through dedicated thermal paths, enabling effective thermal management while maintaining the manufacturing efficiency of wafer-level packaging. The thermal vias act as heat conduits that bridge the thermal gap between chip and substrate.
Solution Approach 2:
The patent implements localized thermal management structures directly beneath high-power chips, including thermal vias and heat sinks positioned at specific hot spots. This local quality approach allows thermal management to be optimized at the chip level without compromising the overall manufacturing efficiency of the wafer-level process. Each chip region receives tailored thermal management based on its power dissipation characteristics.
3Power
If larger packages are used to integrate more chips for high performance computing, then computing performance is improved, but thermal mechanical stress increases
Solution Approach 1:
The patent segments the large package into multiple smaller, independent packaging units on the wafer. Each unit has its own substrate, voltage regulator, and power delivery network, which isolates thermal mechanical stress to local regions. This segmentation allows the overall system to achieve high computing performance through multiple chips while preventing cumulative thermal stress from degrading the entire package.
Solution Approach 2:
The patent modifies the physical parameters of the packaging structure, including substrate thickness, material composition, and thermal via dimensions, to optimize the thermal-mechanical properties. These parameter changes enable the package to accommodate higher power densities and more chips while maintaining stress levels within acceptable limits. The substrate materials and结构设计 are specifically tuned to reduce thermal expansion mismatch and stress concentration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases manufacturing efficiency, enhances power delivery network performance, improves thermal dissipation, and reduces mechanical stress, enabling larger semiconductor devices with better thermal and power management for high-performance computing applications.
Implementation Method 1
liquid cooling channels may be created within the Si or glass substrate to help manage the thermal dissipation of the semiconductor device
Implementation Method 2
Thermal vias may also be provided within the Si or glass substrate for better thermal management
Implementation Method 3
The various chips embedded in the Si or glass substrate may be connected through redistribution layers (RDL) with dense traces
Data Source
AI summary
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. For example, a semiconductor device may include: a substrate; and semiconductor assemblies that are configured to be electrically connected together, each of the semiconductor assemblies including: a first semiconductor chip that is at least partially between a first surface of the substrate and a second surface of the substrate, the first surface facing in a first direction and the second surface facing in a second direction, opposite to the first direction; and a voltage regulator that is on the first surface of the substrate, overlaps with the first semiconductor chip in the first direction, and is configured to be electrically connected to the first semiconductor chip.