Semiconductor Package Corner Dam Structure for Warpage Control

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Solution Overview

Problem

The miniaturization of electronic components leads to issues such as warpage due to non-conductive films in semiconductor packages, which affect the reliability of semiconductor packages.

Innovation Solution

A semiconductor package design that includes a base substrate, a semiconductor chip, a dam structure overlapping the chip's corners, and a filling layer between the substrate and chip, with a molding member covering the chips and filling layers, but not between the substrate and chip, to address warpage and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a non-conductive film is used between multiple semiconductor chips for miniaturization, then the electronic components can be miniaturized and stacked, but warpage occurs in the semiconductor package affecting reliability

Engineering Contradiction:
Improvepackage sizeVSAvoidpackage reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent divides the package structure into multiple layers including base substrate, semiconductor chips, non-conductive films, and molding compound. This segmentation allows each layer to be optimized independently - the non-conductive films enable chip stacking for miniaturization while the molding compound provides external protection, resolving the contradiction between small size and reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structures combining different materials with complementary properties: non-conductive films (polyimide or benzocyclobutene) for electrical insulation and mechanical support between chips, and molding compound for external protection and warpage compensation. This composite approach enables both miniaturization through stacking and maintained reliability

Inventive Principle:
Principle #40Composite materials

2Productivity

If non-conductive films are used to enable chip stacking, then miniaturization is achieved, but warpage is generated affecting product reliability

Engineering Contradiction:
Improvechip stacking capabilityVSAvoidwarpage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a molding compound as an intermediary element that surrounds and protects the stacked chip structure. This molding compound acts as a mediator that compensates for warpage forces generated by the non-conductive films during thermal processing, allowing high-density stacking while maintaining package flatness and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies non-conductive films with specific material properties (polyimide or benzocyclobutene) before chip stacking to preemptively manage thermal expansion differences. These films are selected and positioned in advance to cushion against warpage forces that will occur during subsequent thermal processing, enabling productive stacking while preventing harmful deformation

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12532787B2Semiconductor package
Publication Date: 2026.01.20 SAMSUNG ELECTRONICS CO LTD
  • US12532787B2 patent drawing
  • US12532787B2 patent drawing
  • US12532787B2 patent drawing

AI summary

A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.