Semiconductor Package Layout With Heat Dissipation Structure for Warpage
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Solution Overview
Problem
Package-on-package technology faces thermal stress and warpage issues due to inadequate heat dissipation, as the back side redistribution line and upper semiconductor package are positioned on top of the semiconductor chip, leading to inefficient heat dissipation and thermal stress differences between the upper and lower package structures.
Innovation Solution
Incorporating a heat dissipation structure with through openings on the redistribution substrate, positioning the system-on-chip and memory package side-by-side, and using an encapsulant with a heat dissipation structure that surrounds the semiconductor components, effectively dissipating heat and reducing thermal stress by using materials with higher thermal conductivity like crystalline silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package-on-package technology stacks upper semiconductor package on top of lower semiconductor package, then integration density is improved, but thermal stress and warpage increase due to inadequate heat dissipation
Solution Approach 1:
The patent transitions from a vertical stacking arrangement (package-on-package) to a side-by-side planar arrangement of semiconductor chips on the redistribution substrate. This dimensional change allows heat dissipation structures to be positioned between chips rather than requiring vertical heat paths, effectively resolving the thermal stress issue while maintaining integration density through optimized lateral spacing and heat dissipation pathways.
Solution Approach 2:
The patent introduces a heat dissipation structure as an intermediary element positioned between adjacent semiconductor chips and between the chips and the redistribution substrate. This intermediary structure actively manages thermal energy transfer, preventing heat accumulation that would cause thermal stress and warpage, while allowing the package-on-package integration approach to continue.
2Adaptability or versatility
If back side redistribution line and upper semiconductor package are positioned on top of molded semiconductor chip, then connectivity is improved, but heat dissipation efficiency deteriorates
Solution Approach 1:
The patent extracts the heat dissipation function from the traditional package substrate and creates a separate, dedicated heat dissipation structure. This structure can be positioned optimally between chips and connected to thermal management systems without interfering with the electrical connectivity provided by the redistribution lines on the substrate, thus resolving the conflict between connectivity and heat dissipation.
Solution Approach 2:
The patent segments the package structure into distinct functional zones: a redistribution substrate for electrical connectivity, separate semiconductor chips for computing functions, and dedicated heat dissipation structures for thermal management. This segmentation allows each component to optimize its primary function without compromising the others, enabling both high connectivity and efficient heat dissipation.
3Ease of manufacture
If conventional package structure is used, then manufacturing simplicity is maintained, but warpage deformation increases due to thermal expansion differences
Solution Approach 1:
The patent changes the physical arrangement parameters of the package structure from vertical stacking to side-by-side placement with intermediate heat dissipation structures. This parameter change modifies the thermal expansion stress distribution, reducing warpage deformation while maintaining manufacturing simplicity through standardized chip placement and attachment processes similar to conventional methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances heat dissipation and reduces warpage deformation by utilizing the higher thermal conductivity of materials like silicon, effectively managing thermal expansion differences and improving the overall thermal management within the semiconductor package.
Implementation Method 1
effectively dissipating heat and reducing thermal stress by using materials with higher thermal conductivity like crystalline silicon
Implementation Method 2
effectively managing thermal expansion differences and improving the overall thermal management within the semiconductor package
Data Source
AI summary
A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.