Semiconductor Package Molding Structure to Prevent Warpage and Delamination

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Solution Overview

Problem

Semiconductor packages with high-performance chips experience issues such as warpage due to thermal expansion mismatch, deterioration in underfill resin filling properties, and cracking between the die and molding material during molding processes, particularly when using an interposer.

Innovation Solution

The semiconductor package design includes a substrate with first and second molding members that surround semiconductor chips, featuring recesses with varying widths to enhance bonding strength. The recesses in the first molding member are filled by a second molding member, creating an anchor effect that increases contact area and prevents delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wafer level molding is performed after mounting heterogeneous chips onto a substrate, then high-performance semiconductor chips can be embedded, but warpage occurs due to mismatch in the coefficient of thermal expansion between the interposer and the molding material

Engineering Contradiction:
Improveembedding of high-performance chipsVSAvoidwarpage
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The molding structure is divided into multiple segments: a first molding member that partially surrounds the semiconductor chips and a second molding member that fills recesses in the first molding member. This segmentation allows different materials with different thermal expansion coefficients to be used in different regions, accommodating the interposer and chips while reducing overall warpage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different molding materials are used in different locations: the first molding member uses a material suitable for surrounding the chips, while the second molding member uses a material with thermal expansion properties matched to the interposer. This local quality approach ensures that each region has the appropriate thermal properties to minimize warpage in that specific area.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If wafer level molding is performed with an interposer, then heterogeneous chips can be mounted, but deterioration in the filling properties of an underfill resin occurs

Engineering Contradiction:
Improvemounting of heterogeneous chipsVSAvoidfilling properties of underfill resin
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The recesses are formed in the first molding member before the second molding member is applied. This preliminary action creates predetermined pathways and spaces that guide the underfill resin flow, ensuring proper filling properties and preventing deterioration in the molding process.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If wafer level molding is performed with an interposer, then heterogeneous chip mounting is enabled, but cracking between a die and the molding material occurs

Engineering Contradiction:
Improvemounting of heterogeneous chipsVSAvoidbonding strength between die and molding material
Core Design Contradiction:
Adaptability or versatilityVSStrength

Solution Approach 1:

The second molding member is specifically applied in the recesses of the first molding member, creating a localized bonding interface that accommodates the interposer and chips. This local quality approach ensures that the bonding material is positioned exactly where needed to prevent cracking between the die and molding material.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The molding structure uses a composite of two different molding materials: the first molding member material and the second molding member material. This composite structure provides both mechanical support and thermal expansion matching, preventing cracking while enabling heterogeneous chip mounting.

Inventive Principle:
Principle #40Composite materials

4Device complexity

If a single molding member is used to cover semiconductor chips, then simple structure is maintained, but bonding strength is insufficient leading to delamination

Engineering Contradiction:
Improvemolding structureVSAvoidbonding strength
Core Design Contradiction:
Device complexityVSStrength

Solution Approach 1:

The molding structure is segmented into a first molding member and a second molding member, where the second molding member fills recesses in the first molding member. This segmentation increases the bonding strength through the anchor effect while maintaining relatively simple manufacturing processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second molding member is nested within the recesses of the first molding member, creating an anchor effect that significantly enhances bonding strength. This nesting structure prevents delamination while adding minimal complexity to the overall device structure.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enhances bonding strength between molding members, reducing the risk of delamination and distortion due to thermal or pressure differences, thereby improving the structural integrity of the semiconductor package.

Implementation Method 1

The recesses include first portions, which extend to edges of the first molding member and have a first width, and second portions, which are connected to the first portions and are positioned more inward into the first molding member than the first portions. The second portions have a second width that is greater than the first width, and the second molding member fills at least parts of the recesses.

Methodology Applied
Scientific EffectAnchor effect:

Data Source

PatentUS20250210434A1Semiconductor package
Publication Date: 2025.06.26 SAMSUNG ELECTRONICS CO LTD
  • US20250210434A1 patent drawing
  • US20250210434A1 patent drawing
  • US20250210434A1 patent drawing

AI summary

A semiconductor package includes: a substrate; first semiconductor chips mounted on the substrate; a second semiconductor chip mounted on the substrate; a first molding member covering sides of the first semiconductor chips; and a second molding member covering the first semiconductor chips and the second semiconductor chip. Each of the first semiconductor chip includes a plurality of semiconductor chips that are stacked on each other along a first direction. The first molding member includes recesses extending along the first direction. The recesses include first portions, which extend to edges of the first molding member and have a first width, and second portions, which are connected to the first portions and are positioned more inward into the first molding member than the first portions. The second portions have a second width that is greater than the first width, and the second molding member fills at least parts of the recesses.