Semiconductor Package Structure Reducing Warpage and Delamination
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Solution Overview
Problem
The existing semiconductor package manufacturing process for RF chips with a 5P5M structure is time-consuming and costly, leading to high manufacturing costs and issues such as warpage and delamination due to its great thickness and complex layering requirements.
Innovation Solution
A semiconductor package structure with a multi-layered circuit directly disposed on a first conductive layer, reducing the number of conductive metal layers from five to four, and using a single photomask and photoresist for the conductive layer and multi-layered circuit structure formation to streamline the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 5P5M structure is used to ensure impedance matching, then electrical performance is improved, but manufacturing time increases to about 60 days and cost increases
Solution Approach 1:
The patent extracts and removes unnecessary passivation layers and conductive metal layers from the traditional 5P5M structure. By using a single-layer conductive metal layer combined with a multi-layered circuit structure formed through photolithography, the patent reduces the total layer count while maintaining the essential impedance matching function, thereby significantly reducing manufacturing time and complexity.
Solution Approach 2:
The patent segments the circuit structure into a multi-layered circuit pattern formed on a single conductive metal layer. This segmentation allows the circuit to achieve complex functionality and impedance matching characteristics without requiring multiple thick metal layers, thus reducing manufacturing time while preserving electrical performance.
2Reliability
If a 5P5M structure is used to ensure impedance matching, then electrical performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates redundant layers from the traditional 5P5M structure, keeping only the essential single conductive metal layer combined with a multi-layered circuit pattern. This reduction in layer count directly lowers material consumption and manufacturing steps, thereby reducing production cost while maintaining impedance matching capability.
3Reliability
If a 5P5M structure is used, then impedance matching is achieved, but structure thickness increases causing warpage and delamination
Solution Approach 1:
The patent removes excess passivation and conductive metal layers from the thick 5P5M structure, retaining only the necessary single conductive metal layer with multi-layered circuit pattern. This thinning of the overall structure reduces internal stress accumulation, preventing warpage and delamination issues while preserving the impedance matching function.
Solution Approach 2:
By segmenting the circuit into a multi-layered pattern on a single metal layer, the patent achieves complex electrical functionality without increasing physical thickness. This segmented approach maintains structural integrity and stability while enabling precise impedance control.
4Productivity
If the number of conductive metal layers is reduced from five to four, then manufacturing time and cost are reduced, but impedance matching may be compromised
Solution Approach 1:
The patent compensates for the reduced number of metal layers by implementing a multi-layered circuit structure within the single conductive metal layer. This segmentation of the circuit pattern into multiple functional layers achieves the necessary impedance matching characteristics without requiring multiple thick metal layers, thus maintaining productivity improvements while ensuring electrical performance.
Data Source
AI summary
A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.