Semiconductor Package Warpage Reduction via Dual-Side Carrier Substrates
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Solution Overview
Problem
Conventional packaging processes for semiconductor chips face challenges such as thermal stress-induced cracks, high form factor, loss of known good dies, device leakage, and warpage during the fabrication of integrated circuits, particularly due to the limitations of silicon interposers.
Innovation Solution
The method involves forming a package structure using dual-side processed carrier substrates with conductive pillars and redistribution layers, allowing for efficient electrical connections and reduced warpage, while utilizing a sacrificial layer and conductive foil to facilitate the formation of through vias and redistribution layers, and subsequently debonding the substrates to attach integrated circuit dies with underfill and solder balls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging processes are used with silicon interposers, then electrical connections can be established, but thermal stress-induced cracks occur in solder bumps or solder balls
Solution Approach 1:
An underfill material is introduced as an intermediary substance between the semiconductor chip and package component. This underfill acts as a stress-distributing medium that mitigates thermal stress concentration, preventing cracks in solder bumps or balls while maintaining electrical connections.
Solution Approach 2:
The patent employs composite material structures including the underfill material combined with solder bumps/balls and the interposer substrate. This composite approach creates a multi-material system that balances thermal expansion coefficients and distributes stress more evenly across the assembly.
2Stability of the object's composition
If dual-side processed carrier substrates are used, then warpage is reduced and form factor is minimized, but manufacturing complexity increases
Solution Approach 1:
The carrier substrate is divided into two separate substrates that are processed independently on opposite sides. This segmentation allows each substrate to be optimized and processed separately, then bonded together to form a balanced structure that reduces warpage while maintaining manufacturing feasibility.
Solution Approach 2:
The dual-side processing approach creates a symmetrical final structure through asymmetric processing steps. Each side of the carrier substrate undergoes specific processing tailored to its requirements, then they are bonded to achieve overall structural balance and warpage reduction.
3Adaptability or versatility
If through vias and redistribution layers are formed using sacrificial layers, then electrical routing is improved, but manufacturing steps increase
Solution Approach 1:
Sacrificial layers are deposited and patterned in advance before the final electrical routing structures are formed. These preliminary sacrificial structures serve as templates or placeholders that guide subsequent via formation and material deposition, enabling complex routing patterns to be created through sequential, pre-planned steps.
Solution Approach 2:
Sacrificial layers act as intermediary materials that facilitate the formation of through vias and redistribution layers. These temporary structures enable complex electrical routing to be built up layer by layer, then are selectively removed to create the final routing architecture.
Data Source
AI summary
A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.