Semiconductor Package Layout for Warpage and Heat Dissipation
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Solution Overview
Problem
The challenge is to design a semiconductor package that can accommodate semiconductor chips of different thicknesses without warpage during packaging and improve heat dissipation performance, while ensuring reliable electrical connections and efficient heat transfer.
Innovation Solution
The solution involves a semiconductor package with a substrate that includes a memory semiconductor chip and a logic semiconductor chip of varying thicknesses, where the thinner chip is connected via a wire and the thicker chip via a connection terminal, and a heat sink or heat transfer layer is placed on the thicker chip for enhanced heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips of different thicknesses are integrated into one package, then high capacity and multi-functionality are achieved, but warpage occurs during packaging process
Solution Approach 1:
The semiconductor package is segmented into multiple chips (first semiconductor chip and second semiconductor chip) with different thicknesses, each independently mounted on the substrate. This segmentation allows each chip to be optimized for its specific function while being integrated into a single package, achieving high capacity and multi-functionality without causing warpage through proper distribution and support structures.
2Temperature
If a heat sink or heat transfer layer is added to improve heat dissipation, then thermal management is enhanced, but device complexity increases
Solution Approach 1:
A heat transfer layer is introduced as an intermediary component between the second semiconductor chip and the heat sink. This heat transfer layer efficiently conducts heat away from the chip while maintaining a relatively simple overall structure. The heat transfer layer acts as a mediator that bridges the thermal management needs without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents warpage during packaging, ensures reliable connections between chips, and improves heat dissipation performance by utilizing a heat sink or heat transfer layer on the thicker chip, enhancing the overall reliability and thermal management of the semiconductor package.
Implementation Method 1
an adhesive layer between the first surface of the first substrate and the memory semiconductor package, the adhesive layer attaching the memory semiconductor package to the first surface of the first substrate
Implementation Method 2
a wire extending from an upper surface of the memory semiconductor package to the first substrate, the wire electrically connecting the first substrate and the memory semiconductor package
Implementation Method 3
a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, the first connection terminal electrically connecting the first substrate and the logic semiconductor chip
Implementation Method 4
a heat transfer layer on an upper surface of the molding layer and an upper surface of the second semiconductor chip, the heat transfer layer in contact with the upper surface of the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a first substrate, a memory semiconductor package on a first surface of the first substrate, an adhesive layer between the first surface of the first substrate and the memory semiconductor package, a wire extending from an upper surface of the memory semiconductor package and connected to the first substrate, a logic semiconductor chip on the first surface of the first substrate, a first connection terminal between the first surface of the first substrate and the logic semiconductor chip, and a molding layer, wherein a first height of the memory semiconductor package is smaller than a second height of the logic semiconductor chip, and wherein an uppermost surface of the molding layer and the upper surface of the logic semiconductor chip are coplanar.