Semiconductor Package Metal Layout for Warpage Mitigation
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Solution Overview
Problem
The challenge of warpage in semiconductor packages due to differences in thermal expansion coefficients of individual components is not adequately addressed in existing technologies, impacting the reliability of high integration and high performance semiconductor devices.
Innovation Solution
A semiconductor package design featuring a substrate with specific structural elements, including a metal structure that avoids the corner regions and is positioned to mitigate thermal stress, combined with an underfill material layer and connecting structures to enhance stability and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on a substrate to achieve high integration, then the functionality and performance of the semiconductor device are improved, but warpage occurs due to differences in thermal expansion coefficients of the individual components
Solution Approach 1:
The patent applies local quality by positioning the metal structure specifically in the inner region while excluding corner regions, creating non-uniform thermal expansion compensation across the substrate. This localized approach addresses warpage at specific high-stress areas without affecting the entire substrate uniformly, thereby maintaining high integration capability while improving reliability.
Solution Approach 2:
The patent directly addresses thermal expansion by introducing a metal structure with different thermal expansion properties than the substrate and semiconductor chips. This metal structure is strategically positioned to compensate for the differential thermal expansion that occurs during heating and cooling cycles, thereby reducing warpage and improving package reliability while maintaining multi-chip integration.
2Reliability
If a metal structure is added to the substrate to reduce warpage, then the reliability of the semiconductor package is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct functional regions: an inner region containing the metal structure for warpage control, and corner regions excluded from the metal structure to maintain electrical connectivity. This segmented approach allows the metal structure to be added selectively only where needed for reliability, rather than uniformly across the entire substrate, thereby minimizing the increase in device complexity.
Solution Approach 2:
The metal structure acts as an intermediary element between the substrate and the semiconductor chips, mediating the thermal expansion differences without requiring direct modification of the chips or substrate. This intermediary approach adds a single component layer to address warpage, rather than requiring complex redesigns of existing components, thus limiting the increase in overall device complexity.
3Stability of the object's composition
If the metal structure is positioned to mitigate thermal stress, then the stability of the semiconductor package is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies asymmetry by creating an asymmetric metal structure configuration that is deliberately positioned only in the inner region and excluded from corner regions. This asymmetric positioning is optimized to address the specific thermal stress patterns that occur in multi-chip packages, providing enhanced stability. The asymmetric design simplifies manufacturing by providing clear regional boundaries rather than requiring precise symmetric positioning throughout the entire substrate.
Solution Approach 2:
The patent applies preliminary action by pre-positioning the metal structure in the inner region during substrate fabrication, before the semiconductor chips are mounted. This preliminary placement establishes the thermal stress mitigation framework in advance, allowing subsequent chip mounting and underfill processes to proceed without additional precision requirements for metal structure alignment, thereby reducing overall manufacturing precision demands.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves the reliability of semiconductor packages by reducing warpage and enhancing electrical connectivity, thereby supporting high integration and performance of semiconductor chips.
Implementation Method 1
there is a need to properly control a warpage that occurs due to a difference in thermal expansion coefficients of the individual components that make up the semiconductor package
Data Source
AI summary
A semiconductor package is provided. The semiconductor package includes a substrate comprising an inner region extending in a first direction and a second direction that intersects the first direction, a plurality of corner regions around the inner region, first and third side faces opposite to each other in the first direction, second and fourth side faces opposite to each other in the second direction, and first and second sides that connect the first and third side faces and are opposite to each other in a third direction perpendicular to the first and second directions; a first semiconductor chip on the substrate; a metal structure on the first semiconductor chip and extending over sides of the first semiconductor chip; and a connecting structure on the second side of the substrate, and electrically connected to the first semiconductor chip, in which the metal structure inside the first to fourth side faces of the substrate, and in a region not including the plurality of corner regions among regions.