Semiconductor Package Structure Warpage Mitigation
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Solution Overview
Problem
Conventional semiconductor package structures face warpage issues due to asymmetrical designs and differences in thermal expansion coefficients among material layers, leading to increased manufacturing costs and difficulty in reducing thickness.
Innovation Solution
A semiconductor package structure is designed with a supporter surrounding the chip, an encapsulant between the chip and supporter, and an insulation layer overlapping both in a vertical projection direction, eliminating the need for a carrier or interposer, thus reducing thickness and alleviating warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional semiconductor package uses an asymmetrical structure with thin thickness design, then high density I/O requirements are met, but warpage issues occur due to differences in CTEs among material layers
Solution Approach 1:
The patent applies asymmetry principle by designing a symmetrical package structure with the chip at the center and supporters on both sides, balancing the CTE distribution across the package. This symmetrical arrangement compensates for thermal expansion differences and reduces warpage while maintaining high density I/O through optimized supporter geometry and material selection.
Solution Approach 2:
The patent changes physical parameters by selecting materials with matched CTEs for the supporters and encapsulant, and by optimizing the thickness and geometry of each layer. These parameter adjustments ensure thermal compatibility across layers, reducing differential expansion and preventing warpage during temperature cycling.
2Quantity of substance
If conventional semiconductor packages use interposers and permanent carriers, then high density requirements are met, but manufacturing cost increases and thickness reduction becomes difficult
Solution Approach 1:
The patent extracts and eliminates the interposer and permanent carrier from the package structure, replacing them with simplified supporters that provide the necessary mechanical support and electrical connection functions. This removal of unnecessary components reduces manufacturing cost and simplifies the overall structure while maintaining high density I/O capability through direct chip-to-supporter bonding.
Solution Approach 2:
The supporters in the patent perform multiple functions simultaneously: providing mechanical support, enabling electrical connections, and facilitating heat dissipation. This multi-functionality replaces the separate roles previously fulfilled by interposers and carriers, simplifying the package structure and reducing component count while maintaining high density performance.
3Quantity of substance
If conventional semiconductor packages use asymmetrical thin thickness design, then high density I/O is achieved, but manufacturing cost increases due to permanent carrier usage
Solution Approach 1:
The patent replaces expensive permanent carriers with temporary, removable supporters that can be discarded after serving their purpose during assembly and testing. These temporary supporters enable high density I/O during manufacturing but are not required in the final product, significantly reducing material costs while maintaining manufacturing flexibility and ease of production.
Data Source
AI summary
Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip, and the supporter includes a recessed portion. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.