Semiconductor Package Warpage Control via Symmetrical Molding Compound
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor device packages face warping issues due to diverse coefficients of thermal expansion (CTE) of components, leading to potential electrical connection failures and cracking of conductive bumps during fabrication and reflow processes, which existing technologies only partially mitigate.
Innovation Solution
A semiconductor device package design featuring a substrate and encapsulation layer both made of molding compound, with a dielectric layer sandwiched between upper and lower layers of molding compound, forming a symmetrical structure that counteracts thermal stress and inhibits warping, and a method of fabricating this package involving the formation of conductive columns, dielectric and redistribution structures, and encapsulation layers using molding compound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional FCBGA semiconductor device package is used with components having diverse coefficients of thermal expansion, then the package achieves compact size and electrical connectivity, but warping occurs during fabrication and reflow processes leading to connection failures and conductive bump cracking
Solution Approach 1:
The patent applies asymmetry by strategically positioning the compressive stress layer specifically at the bottom of the redistribution structure rather than distributing stress uniformly. This asymmetric stress distribution counteracts the upward warping forces that occur at the edges of the package during thermal processing, thereby maintaining package flatness and preventing connection failures while preserving electrical connectivity
Solution Approach 2:
The patent changes the physical parameter of stress distribution by introducing a dedicated compressive stress layer with specific mechanical properties. This layer modifies the thermal stress parameters within the redistribution structure, transforming the stress state from tensile (which causes warping) to compressive (which prevents warping), thereby improving reliability during reflow processes
2Length of moving object
If the substrate thickness is reduced to achieve thinner packages, then miniaturization is achieved, but warping control becomes more difficult and connection reliability decreases
Solution Approach 1:
The patent applies local quality by concentrating the compressive stress function in a specific localized region (the compressive stress layer at the bottom of the redistribution structure) rather than requiring uniform thickness throughout the entire package. This localized stress compensation enables thinner overall package design while maintaining connection reliability in the critical bonding regions
3Stability of the object's composition
If existing stress compensation methods are used with limited redistribution structure thickness, then some warping mitigation is achieved, but defects related to warping produced by epoxy molding compound cannot be sufficiently controlled
Solution Approach 1:
The patent applies preliminary action by pre-introducing the compressive stress layer during the redistribution structure formation process, before the epoxy molding compound is applied and before thermal processing occurs. This preemptive stress compensation prepares the structure to resist warping forces that will arise during subsequent manufacturing steps, thereby achieving better manufacturing precision and reducing warping defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The symmetrical molding compound structure effectively balances thermal stress, preventing warping and improving the durability and yield of semiconductor device packages by eliminating the need for an underfill process and enhancing electrical connections.
Implementation Method 1
the diverse coefficients of thermal expansion (CTE) of various components in the semiconductor device package increase the likelihood that components will warp as the semiconductor device package is being fabricated
Data Source
AI summary
A semiconductor device package includes a substrate having a first surface and a second surface facing away from the first surface, a conductive column extending in the substrate between the first surface and the second surface, a dielectric layer on the first surface of the substrate, a redistribution structure provided in the dielectric layer and electrically connected to the conductive column, a semiconductor chip provided above the dielectric layer and electrically connected to the redistribution structure, and an encapsulation layer on the dielectric layer and encapsulating the semiconductor chip. The package is manufactured such that each of the substrate and the encapsulation layer is formed of molding compound.