Semiconductor Package Warpage Prevention Member Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor package devices face warpage issues due to thermal expansion coefficient differences between the interposer and the package substrate, leading to reliability and thermal conductivity challenges.
Innovation Solution
Incorporating a warpage prevention member with a higher thermal expansion coefficient and thickness on the interposer, which is electrically connected to the second package substrate, to mitigate warpage and enhance thermal conductivity by exhausting heat effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to electrically connect the first package substrate and second package substrate, then electrical connectivity is improved, but warpage occurs due to thermal expansion coefficient differences
Solution Approach 1:
The patent applies parameter changes by selecting a warpage prevention member with a thermal expansion coefficient specifically designed to be between that of the interposer and the package substrate. This intermediate parameter value allows the member to act as a thermal expansion buffer, compensating for differential expansion and preventing warpage while maintaining electrical connectivity through the interposer structure.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer structure consisting of the interposer, warpage prevention member, and package substrate. Each layer has distinct material properties, particularly in thermal expansion coefficients, and they are bonded together to form a composite structure that leverages the advantages of each material while mitigating their individual disadvantages regarding warpage.
2Shape
If the warpage prevention member has greater thickness than the interposer, then warpage is suppressed, but the overall package height increases
Solution Approach 1:
The patent utilizes parameter changes by optimizing the thickness of the warpage prevention member to be greater than that of the interposer. This thickness parameter is critical for providing sufficient structural support and warpage resistance. The design accepts the resulting increase in package height as a necessary trade-off to achieve adequate warpage suppression and maintain structural integrity.
3Reliability
If connection terminals extend through the warpage prevention member, then electrical connectivity is maintained, but the structural integrity may be compromised
Solution Approach 1:
The patent applies local quality by providing different structural characteristics in different regions of the warpage prevention member. The member has greater thickness in regions where structural support is needed, while connection terminals are accommodated in specific locations where electrical connectivity is required. This localized variation in thickness and structure allows the member to simultaneously maintain both structural integrity and electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces warpage and improves thermal properties by matching thermal expansion and enhancing heat dissipation, thereby improving the operational reliability and efficiency of semiconductor package devices.
Implementation Method 1
a warpage prevention member and a plurality of connection terminals on the interposer... The warpage prevention member may have a thickness in a direction perpendicular to a top surface of the first package substrate and a thermal expansion coefficient that are greater than those of the interposer
Implementation Method 2
improve thermal properties by matching thermal expansion and enhancing heat dissipation
Data Source
AI summary
A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.


