Semiconductor Package Warpage Reduction via Spacer and Heat Spreader
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face warpage issues due to temperature cycling and differences in thermal expansion properties of materials, limiting package size and thermal performance, which affects the mounting and functionality of IC devices.
Innovation Solution
The semiconductor package design incorporates a spacer and a heat spreading layer with specific thermal expansion coefficients, along with a thermal interlayer or stiffener, to create a robust frame that restricts warpage and enhances thermal performance by providing direct bonding and relieving thermal stresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If package size is increased, then functionality and power handling capability are improved, but warpage magnitude increases
Solution Approach 1:
The patent applies thermal expansion principles by selecting materials with matched coefficients of thermal expansion (CTE). The substrate and encapsulant are chosen to have similar CTE values, reducing differential thermal expansion during temperature cycling. This minimizes warpage in larger packages while maintaining the ability to handle higher power and functionality requirements.
Solution Approach 2:
The patent uses composite material structures combining substrate, encapsulant, and solder balls with carefully selected material properties. This composite approach allows optimization of thermal and mechanical properties to reduce warpage while supporting larger package sizes for enhanced functionality.
2Power
If power density is increased, then functionality is improved, but thermal performance requirements become more stringent
Solution Approach 1:
The patent introduces a thermal interface material or heat spreading layer as an intermediary between the semiconductor die and the substrate. This intermediary improves thermal conduction pathways, enabling higher power density while maintaining acceptable thermal performance by efficiently conducting heat away from the die.
3Ease of manufacture
If substrate and encapsulant materials are selected for other properties, then manufacturing is simplified, but warpage increases due to CTE mismatch
Solution Approach 1:
The patent explicitly addresses CTE matching as a key material selection criterion. By prioritizing materials with matched thermal expansion coefficients, the patent reduces warpage while maintaining manufacturability. This approach balances material selection simplicity with warpage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces warpage and improves thermal performance, allowing for larger package sizes and increased functionality while maintaining reliability and compliance with power limits.
Implementation Method 1
a heat spreading layer, formed over the encapsulant layer and the spacer
Implementation Method 2
differences in the thermal expansion properties of the various materials of the package, e.g., differences in the thermal expansion properties of the substrate and encapsulating material
Data Source
AI summary
A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.