Semiconductor Package Layout for Warpage-Stable Interconnects
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Solution Overview
Problem
Semiconductor packages face challenges in achieving high reliability and yield due to warpage issues caused by uneven resin layer thicknesses, which affect the interconnectivity and stability of the package.
Innovation Solution
A semiconductor package design with a redistribution member, interconnect chip, via structure, and encapsulant, where the thickness of the resin layers above and below the interconnect chip are controlled to be at a similar level, and bump structures with a triple-layer structure are formed to reduce encapsulant thickness, allowing for improved interconnectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the resin layer thickness is increased to encapsulate larger components, then the coverage and protection are improved, but the warpage and reliability deteriorate
Solution Approach 1:
The patent applies different resin layer thicknesses to different regions of the package. Specifically, the first resin layer has a first thickness in a first region and a second thickness in a second region, where the thicknesses are different. This local variation allows adequate encapsulation coverage in areas requiring it while maintaining uniformity in critical areas to prevent warpage, thus resolving the contradiction between coverage and reliability.
2Ease of manufacture
If the bump structure is simplified to reduce manufacturing complexity, then the ease of manufacture is improved, but the electrical connection quality deteriorates
Solution Approach 1:
The patent employs a composite bump structure consisting of multiple layers including a first bump layer, a second bump layer, and a third bump layer, where each layer serves a specific function. The first bump layer provides initial electrical connection, the second bump layer enhances connection quality, and the third bump layer provides additional mechanical and electrical stability. This multi-layer composite approach maintains electrical connection quality while using standard manufacturing processes for each layer, thus resolving the contradiction between manufacturing ease and connection quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The controlled resin layer thickness and triple-layer bump structures enhance the reliability and yield of the semiconductor package by reducing warpage and improving electrical connections, leading to a more stable and efficient semiconductor package.
Implementation Method 1
a first plating layer disposed on the first foil layer
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.