Semiconductor Package Windowed Underfill Layout for Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing Core-SIP semiconductor package technology requires a large horizontal area for mounting DRAM and SOC, and experiences warpage due to differences in coefficients of thermal expansion, leading to packaging size and stability issues.
Innovation Solution
A semiconductor package design featuring a package substrate with a first region and a second region, an outermost insulation layer with a window exposing the first region, a first electronic device mounted on the first region, an underfill member filling the gap between the device and the substrate, and a second electronic device mounted on the outermost insulation layer, which reduces warpage and package size by minimizing thermal expansion differences and eliminating the need for additional dams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Core-SIP technology is used to mount DRAM and SOC side by side, then integration is achieved, but a large horizontal area is required
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side mounting arrangement to a three-dimensional stacked configuration. The SOC is mounted on the package substrate in a first region, while the DRAM is mounted on an upper surface of the package substrate in a second region that is vertically stacked over the first region. This vertical stacking enables integration of multiple devices without increasing the horizontal footprint of the package.
2Adaptability or versatility
If Core-SIP technology is used to mount different components, then integration is achieved, but warpage increases due to differences in coefficients of thermal expansion
Solution Approach 1:
The patent applies different insulation layer thicknesses to different regions of the package substrate. A first insulation layer is formed in a first region where the SOC is mounted, and a second insulation layer is formed in a second region where the DRAM is mounted. The second insulation layer has a greater thickness than the first insulation layer. This local variation in insulation layer thickness compensates for the different coefficients of thermal expansion of the SOC and DRAM, reducing warpage in each specific region while maintaining overall package stability.
3Reliability
If additional dams are added to prevent underfill bleeding, then underfill control is improved, but package size increases
Solution Approach 1:
The patent designs the outermost insulation layer with an opening that serves multiple functions: it allows the underfill member to be applied to the SOC, provides a barrier to prevent underfill from bleeding onto the DRAM or other components, and eliminates the need for separate dam structures. This multi-functional design achieves reliable underfill control without increasing the horizontal package area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces warpage and package size by minimizing thermal expansion differences and eliminating the need for additional dams, while securing the modulus of elasticity of the package, thereby enhancing the stability and compactness of the semiconductor package.
Implementation Method 1
a difference in coefficients of thermal expansion of components of the package may be large. Thus, at an area where SOC is mounted, warpage may increase
Data Source
AI summary
A semiconductor package includes a package substrate including a first region and a second region surrounding the first region, the package substrate including a first insulation layer on an upper surface, an outermost insulation layer on the first insulation layer of the package substrate, the outermost insulation layer defining a window that exposes the first region of the package substrate, a first electronic device on the first region of the package substrate, an underfill member in the window of the outermost insulation layer on the first region of the package substrate, the underfill member at least partially filling a gap between the first electronic device and the package substrate, and a second electronic device on the outermost insulation layer.