Semiconductor Package Molding Structure for Warpage and Void Control
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Solution Overview
Problem
Semiconductor packages face issues with warpage due to differences in coefficient of thermal expansion (CTE) and voids caused by uneven filling rates of molding materials, affecting reliability.
Innovation Solution
The use of multiple molding materials with varying coefficients of thermal expansion and moduli, including a rigid upper-layer structure, a flexible middle-layer structure with interlayers, and a substrate, to control warpage and ensure complete encapsulation, particularly in complex stacking structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a rigid carrier substrate or warpage control structure is introduced to reduce warpage, then warpage is improved, but package volume increases
Solution Approach 1:
The patent changes the material parameters by selecting a molding compound with a coefficient of thermal expansion (CTE) that matches the carrier substrate (both within 2.5-7.0 ppm/°C). This parameter matching eliminates the need for additional warpage control structures, as the thermal expansion compatibility naturally prevents warpage during temperature variations, thereby maintaining compact package volume.
Solution Approach 2:
The patent employs a composite structure where the molding compound and carrier substrate are designed as thermally compatible materials. By ensuring both materials have CTE values within the same range (2.5-7.0 ppm/°C), they form a composite system that resists warpage through thermal expansion compatibility rather than requiring separate rigid support structures.
2Speed
If EMC fills in a faster rate at a face of the die without bumps than at a face with bumps, then filling speed is improved, but voids occur due to filling delay under the die
Solution Approach 1:
The patent modifies the viscosity parameter of the molding compound to a specific range (100-5000 Pa·s at processing temperature) that enables uniform filling rate across different die surfaces. This viscosity optimization ensures the material flows at comparable rates whether the die surface has bumps or not, preventing filling delays and void formation while maintaining efficient encapsulation.
3Stability of the object's composition
If multiple molding materials with different CTEs are used to control warpage, then warpage control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies homogeneity by using molding compound and carrier substrate materials with matched thermal expansion properties (both within 2.5-7.0 ppm/°C). This material uniformity in terms of thermal behavior simplifies the manufacturing process compared to using multiple materials with different CTEs, as it eliminates the need for complex multi-material molding processes while still achieving effective warpage control through thermal compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warpage and voids, enhancing the reliability of semiconductor packages by absorbing thermal stress and ensuring uniform filling, thereby improving device reliability and reducing the risk of delamination and fracture.
Implementation Method 1
a middle-layer structure including at least one interlayer, the at least one inter layer being formed of a second molding material different from the first molding material, the middle-layer structure being between the lower-layer structure and the upper-layer structure and filling a space between the lower-layer structure and the upper-layer structure
Implementation Method 2
the at least one inter layer being formed of a second molding material different from the first molding material, the middle-layer structure being between the lower-layer structure and the upper-layer structure and filling a space between the lower-layer structure and the upper-layer structure
Data Source
AI summary
Provided are semiconductor packages and methods of manufacturing the same. A semiconductor package includes a lower-layer structure including a substrate, a first chip including bumps on an active surface thereof, the first chip being electrically connected to the substrate via the bumps, an upper-layer structure formed of a first molding material, the first molding material covering an inactive surface of the first chip opposite and surrounding at least a portion of a lateral surface of the first chip, the inactive surface of the first chip being opposite to the active surface of the first chip, and a middle-layer structure including at least one interlayer, the at least one inter layer being formed of a second molding material different from the first molding material, the middle-layer structure being between the lower-layer and upper-layer structures and filling a space between the lower-layer and upper-layer structures.