Semiconductor Package Wiring Layout for Substrate Warpage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization and weight reduction of electronic components lead to challenges in controlling the warpage of semiconductor package substrates, resulting in potential cracks due to warpage differences between mounting and non-mounting areas.
Innovation Solution
A semiconductor package design that includes a substrate with a mounting area for the semiconductor chip and a non-mounting area, where the substrate features a wiring configuration with specific width variations to reduce shear stress and minimize warpage differences, thereby preventing cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the substrate thickness is reduced for miniaturization, then the size and weight of the semiconductor package are reduced, but the warpage control becomes more difficult and cracks may occur
Solution Approach 1:
The patent applies local quality by varying the wiring width at specific locations. The wiring width is increased at the boundary between mounting and non-mounting areas to locally enhance stiffness where warpage differential is most problematic, while maintaining thinner overall substrate thickness for miniaturization.
Solution Approach 2:
The patent changes the geometric parameter of the wiring (width) to control mechanical properties. By adjusting the wiring width parameter at critical locations, the substrate's resistance to warpage is modified locally without changing the overall substrate thickness, thus maintaining miniaturization while improving reliability.
2Strength
If the mounting area is made stiff to support the semiconductor chip, then the chip mounting stability is improved, but warpage difference occurs between the mounting area and the non-mounting area
Solution Approach 1:
The patent makes different parts of the substrate have different wiring widths. The wiring width is increased specifically at the boundary region between mounting and non-mounting areas, creating local stiffness enhancement where needed to balance the warpage differential caused by the stiff mounting area.
Solution Approach 2:
The patent introduces asymmetry in the wiring configuration by having different wiring widths in different regions. The wiring width is asymmetrically increased at the boundary area to compensate for the stiffness mismatch between mounting and non-mounting areas, rather than making the entire substrate uniformly stiff.
Data Source
AI summary
A semiconductor package includes a substrate; a semiconductor chip on a first surface of the substrate; and a plurality of external connection terminals on a second surface of the substrate that is opposite to the first surface. The substrate includes a plurality of wirings configured to electrically connect the semiconductor chip and the plurality of external connection terminals. The plurality of wirings includes a first wiring, and the first wiring includes a first portion and a second portion connected to each other, the second portion overlapping an edge of the semiconductor chip in a vertical direction that is perpendicular to the first surface of the substrate. A second width of the second portion is greater than a first width of the first portion.