Semiconductor Package with Inter-Chip Waveguides for I/O Bottlenecks
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Solution Overview
Problem
As the minimum feature size in integrated circuit dies decreases, electrical input/output (I/O) interconnects become bottlenecks in data transmission rate, necessitating enhanced packaging techniques such as fanout technology and optical I/O interconnects to improve performance and reduce package size and transmission costs.
Innovation Solution
The implementation of fanout technology and optical I/O interconnects in semiconductor packaging, which involves forming a semiconductor package with electric integrated circuit dies and photoelectric integrated circuit dies, using a redistribution circuit layer and inter-chip waveguides for optical communication, and stacking power sources over the dies to achieve a compact package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical I/O interconnects become bottlenecks in data transmission rate
Solution Approach 1:
The patent replaces electrical interconnects with optical interconnects using waveguides. The waveguides transmit data optically between chips, substituting the electrical signal transmission mechanism with an optical one, thereby achieving higher data transmission rates without being constrained by electrical interconnect bottlenecks
Solution Approach 2:
The patent transitions from planar electrical interconnects to three-dimensional optical waveguide structures. The waveguides extend vertically through the substrate, enabling data transmission in the vertical dimension rather than only horizontally, which increases I/O bandwidth and transmission capacity
2Speed
If fanout technology and optical I/O interconnects are implemented, then data transmission rate and I/O bandwidth are enhanced, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into integrated structures. The waveguides are formed within the substrate itself rather than as separate components, merging the interconnect function with the substrate structure. Power sources are stacked over the dies, combining power delivery with the optical interconnect structure, thereby reducing overall packaging complexity despite the advanced functionality
Solution Approach 2:
The waveguide structure serves multiple functions: it provides optical data transmission pathways, acts as a structural framework for stacking power sources, and enables both horizontal and vertical signal routing. This multi-functionality reduces the need for separate dedicated structures for each function, simplifying the overall device architecture
3Quantity of substance
If optical I/O interconnects are used, then I/O bandwidth increases, but manufacturing precision requirements increase
Solution Approach 1:
The waveguides are formed within the substrate before the chips are mounted. This preliminary formation of the optical interconnect structure allows for pre-alignment and integration with the substrate's electrical interconnects, reducing the precision requirements for subsequent chip mounting operations. The waveguides are positioned and configured in advance, establishing a stable framework for later component assembly
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data transmission rate and I/O bandwidth, reduces package size, and lowers transmission costs by effectively addressing the limitations of traditional electrical interconnects.
Implementation Method 1
an inter-chip waveguide disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide
Data Source
AI summary
A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.