Stacked Semiconductor Package with Substrate Window for Pad Access
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Solution Overview
Problem
There is a challenge in manufacturing semiconductor packages with higher capacities and mounting multiple semiconductor chips in a limited space without increasing the overall thickness, while also improving electrical characteristics and preventing short circuits due to interference among wires or interconnections.
Innovation Solution
A semiconductor package design featuring a substrate with a window for exposing bonding pads of a center semiconductor chip, edge-pad type first semiconductor chips attached face-down on the substrate, and conductive connection members, along with an encapsulation member to protect the chips and reduce interference, allowing for improved signal transfer and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are mounted in a limited space to increase capacity, then the chip capacity increases, but the overall thickness of the package increases
Solution Approach 1:
The patent transitions from horizontal mounting to vertical stacking of semiconductor chips, utilizing the thickness dimension to accommodate multiple chips. This allows increased chip capacity while maintaining a compact package footprint, effectively resolving the contradiction between quantity and thickness.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within a single package, with each chip positioned on top of the previous one. This nesting approach enables high-density integration without proportionally increasing the package thickness.
2Quantity of substance
If multiple semiconductor chips are embedded in a single package to increase capacity, then the chip capacity increases, but the electrical characteristics deteriorate due to interference among wires or interconnections
Solution Approach 1:
The patent extracts the bonding pads of the center semiconductor chip through a window formed in the substrate, separating the electrical connection path from the interfering interconnection wires. This extraction reduces electromagnetic interference and improves signal integrity, resolving the contradiction between capacity and electrical characteristics.
Solution Approach 2:
The window structure acts as an intermediary that provides a dedicated electrical connection path for the center chip's bonding pads, isolating it from interference by surrounding interconnection wires while maintaining electrical functionality.
3Length of stationary object
If the overall thickness of the package is reduced to maintain compact size, then the package size decreases, but the heat dissipation capability deteriorates
Solution Approach 1:
The patent utilizes vertical thermal pathways through the stacked chip structure and substrate to dissipate heat in the thickness dimension, enabling effective heat management in a thin package configuration.
Solution Approach 2:
The patent provides enhanced heat dissipation pathways at critical locations, such as through the window structure and substrate connections, allowing localized thermal management that maintains overall package thinness while ensuring adequate heat dissipation from hot spots.
Data Source
AI summary
A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.