Semiconductor Package Bonding Wire Layout for Lower Crosstalk

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Solution Overview

Problem

In semiconductor packages with stacked semiconductor chip stacks, the loop shape of bonding wires connected to ground/power pads and/or input/output pads causes crosstalk between signals, leading to signal deterioration.

Innovation Solution

The semiconductor package design includes alternately disposed upper bonding wires connected to ground/power and input/output pads, using a reverse bonding method to minimize loop inclination and crosstalk, with specific bending angles and positions to optimize signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding wires are arranged in a loop shape connecting ground/power pads and input/output pads, then electrical connectivity is achieved, but crosstalk between adjacent bonding wires occurs causing signal deterioration

Engineering Contradiction:
Improvesignal integrityVSAvoidcrosstalk between bonding wires
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by reversing the bonding method between adjacent bonding wires: odd-numbered wires use ball-bonding at both ends while even-numbered wires use stitch-bonding at both ends. This asymmetric configuration breaks the symmetric loop structure that causes crosstalk, reducing near-end crosstalk by 4.3 dB and far-end crosstalk by 1.8 dB while maintaining electrical connectivity.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If conventional bonding methods are used, then manufacturing simplicity is maintained, but signal transmission quality deteriorates due to crosstalk

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidbonding wire configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bonding wire configuration into two distinct groups: odd-numbered wires with ball-bonding at both ends and even-numbered wires with stitch-bonding at both ends. This segmentation allows each group to have optimized bonding characteristics, reducing overall crosstalk while maintaining manufacturing feasibility through systematic differentiation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent inverts the conventional approach by using different bonding methods for adjacent wires instead of uniform bonding. Specifically, it reverses the bonding type (ball vs. stitch) between neighboring wires, which unexpectedly reduces crosstalk by creating asymmetric current paths and reducing electromagnetic coupling between adjacent wires.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces signal deterioration by improving near-end crosstalk (NEXT) from -17.5 dB to -21.8 dB and far-end crosstalk (FEXT) from -21.5 dB to -23.3 dB, enhancing signal integrity.

Implementation Method 1

The lower bonding wires are ball-bonded to the first chip pads and are stich-bonded to the first substrate pads

Methodology Applied
Scientific EffectBall bonding:

Implementation Method 2

The lower bonding wires are ball-bonded to the first chip pads and are stich-bonded to the first substrate pads

Methodology Applied
Scientific EffectStitch bonding:

Implementation Method 3

The upper bonding wires are stich-bonded to the second chip pads and are ball-bonded to the second substrate pads

Methodology Applied
Scientific EffectStitch bonding:

Implementation Method 4

The upper bonding wires are stich-bonded to the second chip pads and are ball-bonded to the second substrate pads

Methodology Applied
Scientific EffectBall bonding:

Data Source

PatentUS12482789B2Semiconductor package
Publication Date: 2025.11.25 SAMSUNG ELECTRONICS CO LTD
  • US12482789B2 patent drawing
  • US12482789B2 patent drawing
  • US12482789B2 patent drawing

AI summary

In some embodiments, a semiconductor package includes a package substrate that includes a first surface, a second surface that is opposite to the first surface, first substrate pads disposed on the first surface in a first row, and second substrate pads disposed on the first surface in a second row. The semiconductor package further includes a first semiconductor chip that includes first chip pads, lower bonding wires configured to respectively couple the first chip pads and the first substrate pads, a second semiconductor chip that includes second chip pads, upper bonding wires configured to respectively couple the second chip pads and the second substrate pads, and an encapsulant disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip. The lower bonding wires are ball-bonded to the first chip pads and stich-bonded to the first substrate pads.